4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Mobile LPDDR2 SDRAM
MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,
MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,
MT42L256M64D4
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade
(MHz)
(Mb/s/pin)
-18
-25
-3
533
400
333
1066
800
667
RL
8
6
5
WL
4
3
2
t
RCD/
t
RP
1
Options
• V
DD2
: 1.2V
• Configuration
– 32 Meg x 16 x 8 banks x 1 die
– 16 Meg x 32 x 8 banks x 1 die
– 16 Meg x 32 x 8 banks x 2 die
– 32 Meg x 16 x 8 banks x 4 die
– 16 Meg x 32 x 8 banks x 2 die
– 16 Meg x 32 x 8 banks x 3 die
– 16 Meg x 32 x 8 banks x 4 die
• Device type
– LPDDR2-S4, 1 die in package
– LPDDR2-S4, 2 die in package
– LPDDR2-S4, 3 die in package
– LPDDR2-S4, 4 die in package
• FBGA “green” package
– 134-ball FBGA (10mm x
11.5mm)
– 168-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 220-ball FBGA (14mm x 14mm)
– 240-ball FBGA (14mm x 14mm)
– 253-ball FBGA (11mm x 11mm)
• Timing – cycle time
– 1.875ns @ RL = 8
– 2.5ns @ RL = 6
– 3.0ns @ RL = 5
• Operating temperature range
– From –30°C to +85°C
– From –40°C to +105°C
• Revision
Note:
Marking
L
256M16
128M32
256M32
512M32
128M64
192M64
256M64
D1
D2
D3
D4
GU, GV
LF, LG
LH, LK, LL, LM
LD, MP
MC
EU, EV
-18
-25
-3
WT
AT
:A
Typical
Typical
Typical
1. For Fast
t
RCD/
t
RP, contact factory.
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4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN
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Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Table 2: Single Channel S4 Configuration Addressing
256 Meg x 16
Architecture
Die
configuration
Row addressing
Column
addressing
Number of die
Die per rank
CS0#
CS1#
Ranks per channel
1
Note:
CS0#
CS1#
CS0#
CS1#
Figure 4 (page 16)
128 Meg x 32
Figure 4 (page 16)
256 Meg x 32
Figure 5 (page 17)
512 Meg x 32
Figure 9 (page 21)
32 Meg x 16 x 8 banks
n/a
16K (A[13:0])
2K (A[10:0])
n/a
1
1
0
1
16 Meg x 32 x 8 banks
n/a
16K (A[13:0])
1K (A[9:0])
n/a
1
1
0
1
16 Meg x 32 x 8 banks
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
2
1
1
2
32 Meg x 16 x 8 banks
32 Meg x 16 x 8 banks
16K (A[13:0])
2K (A[10:0])
2K (A[10:0])
4
2
2
2
1. A channel is a complete LPDRAM interface, including command/address and data pins.
Table 3: Dual Channel S4 Configuration Addressing
128 Meg x 64
Architecture
Die configuration
Row addressing
Column addressing
Number of die
Die per rank
CS0#
CS1#
Ranks per channel
1
Channel A
Channel B
Note:
CS0#
CS1#
Figure 6 (page 18)
192 Meg x 64
Figure 8 (page 20)
256 Meg x 64
Figure 7 (page 19)
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
n/a
2
1
0
1
1
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
3
1
1 = Channel A
0 = Channel B
2
1
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
4
1
1
2
2
1. A channel is a complete LPDRAM interface, including command/address and data pins.
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Figure 1: 4Gb LPDDR2 Part Numbering
MT
42
L
128M32
D1
GU
-25
WT
:A
Micron Technology
Product Family
42 = Mobile LPDDR2 SDRAM
Design Revision
:A = First generation
Operating Temperature
WT = –30°C to +85°C
AT = –40°C to +105°C
Operating Voltage
L = 1.2V
Cycle Time
Configuration
256M16 = 256 Meg x 16
128M32 = 128 Meg x 32
256M32 = 256 Meg x 32
512M32 = 512 Meg x 32
128M64 = 128 Meg x 64
192M64 = 192 Meg x 64
256M64 = 256 Meg x 64
-18 = 1.875ns,
t
CK RL = 8
-25 = 2.5ns,
t
CK RL = 6
-3 = 3.0ns,
t
CK RL = 5
Package Codes
GU, GV
LF, LG
LD, MP
= 134-ball FBGA, 10mm x 11.5mm
= 168-ball FBGA, 12mm x 12mm
= 220-ball FBGA, 14mm x 14mm
= 240-ball FBGA, 14mm x 14mm
= 253-ball FBGA, 11mm x 11mm
LH, LK, LL, LM = 216-ball FBGA, 12mm x 12mm
MC
EU, EV
Addressing
D1 = LPDDR2, 1 die
D2 = LPDDR2, 2 die
D3 = LPDDR2, 3 die
D4 = LPDDR2, 4 die
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
Table 4: Package Codes and Descriptions
Package
Code
GU
GV
LF
LG
LH
LL
LM
LK
MP
LD
MC
EU
EV
Notes:
Ball Count
134
134
168
168
216
216
216
216
220
220
240
253
253
# Ranks
1
2
1
2
1
1
2
2
1
2
1
1
2
# Channels
1
1
1
1
1
2
2
1
2
2
2
2
2
Size (mm)
10 x 11.5 x 0.7, 0.65 pitch
10 x 11.5 x 0.85, 0.65 pitch
12 x 12 x 0.75, 0.5 pitch
12 x 12 x 0.8, 0.5 pitch
12 x 12 x 0.65, 0.4 pitch
12 x 12 x 0.8, 0.4 pitch
12 x 12 x 1.0, 0.4 pitch
12 x 12 x 0.8, 0.4 pitch
14 x 14 x 0.8, 0.5 pitch
14 x 14 x 1.0, 0.5 pitch
14 x 14 x 0.8, 0.5 pitch
11 x 11 x 0.9, 0.5 pitch
11 x 11 x 1.2, 0.5 pitch
Die per
Package
SDP
DDP
SDP
DDP
SDP, Channel B
DDP
QDP
DDP Channel B
DDP
QDP
DDP
DDP
QDP
Solder Ball
Composition
LF35 (w/OSP)
LF35 (w/OSP)
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
LF35 (w/OSP)
LF35 (w/OSP)
1. SDP = single-die package, DDP = dual-die package, QDP = quad-die package.
2. Solder ball material: LF35 with Cu OSP ball pads (98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni)
SAC305 (96.5% Sn, 3% Ag, 0.5% Cu
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4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Contents
General Description ....................................................................................................................................... 11
General Notes ............................................................................................................................................ 11
I
DD
Specifications ........................................................................................................................................... 12
Package Block Diagrams ................................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Ball Assignments and Descriptions ................................................................................................................. 34
Functional Description ................................................................................................................................... 43
Power-Up ....................................................................................................................................................... 44
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 46
Power-Off ....................................................................................................................................................... 46
Uncontrolled Power-Off .............................................................................................................................. 47
Mode Register Definition ................................................................................................................................ 47
Mode Register Assignments and Definitions ................................................................................................ 47
ACTIVATE Command ..................................................................................................................................... 58
8-Bank Device Operation ............................................................................................................................ 58
Read and Write Access Modes ......................................................................................................................... 59
Burst READ Command ................................................................................................................................... 59
READs Interrupted by a READ ..................................................................................................................... 66
Burst WRITE Command .................................................................................................................................. 66
WRITEs Interrupted by a WRITE ................................................................................................................. 69
BURST TERMINATE Command ...................................................................................................................... 69
Write Data Mask ............................................................................................................................................. 71
PRECHARGE Command ................................................................................................................................. 72
READ Burst Followed by PRECHARGE ......................................................................................................... 73
WRITE Burst Followed by PRECHARGE ....................................................................................................... 74
Auto Precharge ........................................................................................................................................... 75
READ Burst with Auto Precharge ................................................................................................................. 75
WRITE Burst with Auto Precharge ............................................................................................................... 76
REFRESH Command ...................................................................................................................................... 78
REFRESH Requirements ............................................................................................................................. 84
SELF REFRESH Operation ............................................................................................................................... 86
Partial-Array Self Refresh – Bank Masking .................................................................................................... 87
Partial-Array Self Refresh – Segment Masking .............................................................................................. 88
MODE REGISTER READ ................................................................................................................................. 89
Temperature Sensor ................................................................................................................................... 91
DQ Calibration ........................................................................................................................................... 93
MODE REGISTER WRITE Command ............................................................................................................... 95
MRW RESET Command .............................................................................................................................. 95
MRW ZQ Calibration Commands ................................................................................................................ 96
ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 98
Power-Down .................................................................................................................................................. 98
Deep Power-Down ........................................................................................................................................ 105
Input Clock Frequency Changes and Stop Events ............................................................................................ 106
Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 106
Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 107
NO OPERATION Command ........................................................................................................................... 107
Simplified Bus Interface State Diagram ....................................................................................................... 107
Truth Tables .................................................................................................................................................. 109
Electrical Specifications ................................................................................................................................. 117
Absolute Maximum Ratings ....................................................................................................................... 117
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4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Input/Output Capacitance ......................................................................................................................... 117
Electrical Specifications – I
DD
Specifications and Conditions ........................................................................... 118
AC and DC Operating Conditions ................................................................................................................... 121
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 123
V
REF
Tolerances ......................................................................................................................................... 124
Input Signal .............................................................................................................................................. 125
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 127
Single-Ended Requirements for Differential Signals .................................................................................... 128
Differential Input Crosspoint Voltage ......................................................................................................... 130
Input Slew Rate ......................................................................................................................................... 131
Output Characteristics and Operating Conditions ........................................................................................... 131
Single-Ended Output Slew Rate .................................................................................................................. 132
Differential Output Slew Rate ..................................................................................................................... 133
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 135
Output Driver Impedance .............................................................................................................................. 135
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 136
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 137
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 137
Clock Specification ........................................................................................................................................ 141
t
CK(abs),
t
CH(abs), and
t
CL(abs) ................................................................................................................ 142
Clock Period Jitter .......................................................................................................................................... 142
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 142
Cycle Time Derating for Core Timing Parameters ........................................................................................ 143
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 143
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 143
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 143
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 144
Refresh Requirements .................................................................................................................................... 145
AC Timing ..................................................................................................................................................... 146
CA and CS# Setup, Hold, and Derating ........................................................................................................... 152
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 159
Revision History ............................................................................................................................................ 166
Rev. M – 10/12 ........................................................................................................................................... 166
Rev. L – 08/12 ............................................................................................................................................ 166
Rev. K – 07/12 ............................................................................................................................................ 166
Rev. J – 07/12 ............................................................................................................................................. 166
Rev. I – 05/12 ............................................................................................................................................. 166
Rev. H – 04/12 ............................................................................................................................................ 166
Rev. G – 04/12 ............................................................................................................................................ 166
Rev. F – 03/12 ............................................................................................................................................ 166
Rev. E – 02/12 ............................................................................................................................................ 166
Rev. D – 12/11 ............................................................................................................................................ 167
Rev. C – 12/11 ............................................................................................................................................ 167
Rev. B – 05/11 ............................................................................................................................................ 167
Rev. A – 02/11 ............................................................................................................................................ 167
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. M 10/12 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
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