PCF8598C-2
1024
×
8-bit CMOS EEPROM with I
2
C-bus interface
Rev. 06 — 22 October 2004
Product data
1. Description
The PCF8598C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 8 kbits (1024
×
8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I
2
C-bus. Up to two
PCF8598C-2 devices may be connected to the I
2
C-bus. Chip select is accomplished
by one address input (A2).
Timing of the E/W cycle is carried out internally, thus no external components are
required. Programming Time Control (PTC), Pin 7, must be connected to either V
DD
or left open-circuit. There is an option of using an external clock for timing the length
of an E/W cycle.
2. Features
s
Low power CMOS:
x
2.0 mA maximum operating current
x
maximum standby current 10
µA
(at 6.0 V), typical 4
µA
s
Non-volatile storage of 8 kbits organized as 1024
×
8-bit
s
Single supply with full operation down to 2.5 V
s
On-chip voltage multiplier
s
Serial input/output I
2
C-bus
s
Write operations:
x
byte write mode
x
8-byte page write mode (minimizes total write time per byte)
s
Read operations:
x
sequential read
x
random read
s
Internal timer for writing (no external components)
s
Internal power-on reset
s
0 kHz to 100 kHz clock frequency
s
High reliability by using a redundant storage code
s
Endurance: 1,000,000 Erase/Write (E/W) cycles at T
amb
= 22
°C
s
10 years non-volatile data retention time
Philips Semiconductors
PCF8598C-2
1024
×
8-bit CMOS EEPROM with I
2
C-bus interface
s
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
s
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
s
Offered in DIP8 and SO8 packages.
3. Quick reference data
Table 1:
Symbol
V
DD
I
DDR
Quick reference data
Parameter
supply voltage
supply current read
f
SCL
= 100 kHz
V
DD
= 2.5 V
V
DD
= 6 V
I
DDW
supply current E/W
f
SCL
= 100 kHz
V
DD
= 2.5 V
V
DD
= 6 V
I
DD(stb)
standby supply current V
DD
= 2.5 V
V
DD
= 6 V
-
-
-
-
-
-
-
-
0.6
2.0
3.5
10
mA
mA
µA
µA
-
-
-
-
60
200
µA
µA
Conditions
Min
2.5
Typ
-
Max
6.0
Unit
V
4. Ordering information
Table 2:
Ordering information
Package
Name
PCF8598C-2P/02
PCF8598C-2T/02
DIP8
SO8
Description
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package 8 leads;
body width 7.5 mm
Version
SOT97-1
SOT176-1
Type number
4.1 Ordering options
Table 3:
Ordering options
Topside mark
PCF8598C-2
8598C-2
Type number
PCF8598C-2P/02
PCF8598C-2T/02
9397 750 14219
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 22 October 2004
2 of 21
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9397 750 14219
Product data
I
2
C-BUS CONTROL LOGIC
WP
1
BYTE
COUNTER
SEQUENCER
3
4
EE
CONTROL
ADDRESS
HIGH
REGISTER
DIVIDER
( 128)
BYTE
LATCH
(8 bytes)
ADDRESS
POINTER
8
EEPROM
7
TIMER
( 16)
PTC
OSCILLATOR
002aaa254
PCF8598C-2
5. Block diagram
SCL
6
Philips Semiconductors
SDA
5
INPUT
FILTER
n
Rev. 06 — 22 October 2004
ADDRESS
SWITCH
SHIFT
REGISTER
A2
3
TEST MODE DECODER
VDD
8
POWER-ON-RESET
4
VSS
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
1024
×
8-bit CMOS EEPROM with I
2
C-bus interface
PCF8598C-2
3 of 21
Fig 1. Block diagram.
Philips Semiconductors
PCF8598C-2
1024
×
8-bit CMOS EEPROM with I
2
C-bus interface
6. Pinning information
6.1 Pinning
WP
1
8 V DD
7
PCF8598C-2
6
5
002aaa255
N.C. 2
A2 3
VSS 4
PTC
SCL
SDA
Fig 2. Pin configuration.
6.2 Pin description
Table 4:
Symbol
WP
N.C.
A2
V
SS
SDA
SCL
PTC
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
Description
active-HIGH write-protection input
not connected
address input 2
negative supply voltage
serial data input/output (I
2
C-bus)
serial clock input (I
2
C-bus)
programming time control output
positive supply voltage
9397 750 14219
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 22 October 2004
4 of 21
Philips Semiconductors
PCF8598C-2
1024
×
8-bit CMOS EEPROM with I
2
C-bus interface
7. Device addressing
Table 5:
Selection
Bit
Device
[1]
Device address code
Device code
b7
[1]
1
b6
0
b5
1
b4
0
b3
A2
Chip Enable
b2
A1
b1
A0
R/W
b0
R/W
The Most Significant Bit (MSB) ‘b7’ is sent first.
A2 is the hardware selectable pin, A1 and A0 are software selectable pins.
A system could have up to two PCF8598C-2 devices on the same I
2
C-bus, equivalent
to a 16 kbit EEPROM, or 2 devices of 1024 bytes of memory, or 8 pages of 256 bytes
of memory.
A1 and A0 select a 256 byte page (one of the four pages available) on the selected
device. The device is selected by bit A2.
Figure 3
shows the various address and
page combinations.
I
2
C-BUS
PCF8598C-2
DEVICE 1
256-BYTE PAGE 4
256-BYTE PAGE 3
256-BYTE PAGE 2
256-BYTE PAGE 1
PCF8598C-2
DEVICE 2
256-BYTE PAGE 4
256-BYTE PAGE 3
256-BYTE PAGE 2
256-BYTE PAGE 1
002aaa256
A2
0
0
0
0
A1
1
1
0
0
A0
1
0
1
0
1
1
1
1
1
1
0
0
1
0
1
0
Fig 3. Device addressing.
9397 750 14219
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 22 October 2004
5 of 21
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