INTEGRATED CIRCUITS
DATA SHEET
PCF8801
LCD driver for 140
×
2 segments
Product specification
File under Integrated Circuits, IC12
2000 Feb 04
Philips Semiconductors
Product specification
LCD driver for 140
×
2 segments
FEATURES
•
Single-chip LCD controller/driver
•
Fixed backplane multiplexing at a rate of 1 : 2
•
Internal LCD bias generation (0.5V
DD
)
•
140 segment outputs configured to drive seven
40-segment characters
•
On-chip oscillator with one external resistor
•
Wide power supply range (2.7 V up to 5.5 V)
•
Low power consumption
•
Compatible with most microprocessors/microcontrollers
•
1 MHz serial bus interface (280-bit shift register)
•
Easily cascaded for large LCD applications (two
cascade directions possible)
•
Compatible with chip-on-glass technology
•
Manufactured by silicon gate CMOS process.
GENERAL DESCRIPTION
The PCF8801 is a peripheral device which interfaces a
multiplexed Liquid Crystal Display (LCD) having two
backplanes and up to 140 segments. It generates drive
signals at a multiplex rate of 1 : 2 allowing seven
40-segment (5 x 8) characters to be driven.
ORDERING INFORMATION
TYPE
NUMBER
PCF8801U
PACKAGE
NAME
−
chip with bumps in tray
DESCRIPTION
PCF8801
The chip can easily be cascaded for larger LCD
applications, and the direction of the information flow in the
cascade can be selected. The PCF8801 is compatible with
most microprocessors/microcontrollers and
communicates via a serial bus interface comprising a
280-bit shift register.
The outputs are multiplexed by a clock signal generated by
the internal oscillator which needs only one external
resistor. Cascade applications only require the clock signal
to be generated by the first device with the internal
oscillators in the other devices disabled.
The PCF8801 is designed for chip-on-glass applications.
It has a narrow package with raised points (bumps) for
easy assembly on to LCD glass.
VERSION
−
2000 Feb 04
2
Philips Semiconductors
Product specification
LCD driver for 140
×
2 segments
BLOCK DIAGRAM
PCF8801
handbook, full pagewidth
LDPI
LDNI
DI1
DO1
DIR
CLKI
CLKO
DO2
DI2
LCD BIAS GENERATOR
IO1_1
OM1
SH1_1
280-BIT
IO140_2
OM140
SH140_2
BI-
280-BIT
ROUTING
OUTPUT
DIRECTIONAL
OUTPUT
BLOCK
MULTIPLEXER
SHIFT
REGISTER
REGISTER
LDPO
LDNO
OUTPUT
DRIVERS
S1
S140
÷
2
OSCI
OSCO
INT_OSCO
INTERNAL OSCILLATOR
REXT
FRAME GENERATOR
COMMON
M
VMID
COM1
BACKPLANE DRIVERS
COM2
÷
4
PCF8801
POWER-ON-RESET
RESET
MGL915
T1 T2 T3
VSS1 VSS3 VSS5
VSS2 VSS4
VDD1 VDD3 VDD5
VDD2 VDD4
Fig.1 Block diagram.
2000 Feb 04
3
Philips Semiconductors
Product specification
LCD driver for 140
×
2 segments
PINNING
SYMBOL
V
DD1
to V
DD4
V
SS1
to V
SS4
V
DD5
V
SS5
REXT
RESET
T1 to T3
COM1_1, COM1_2
COM2_1, COM2_2
DIR
S1 to S140
DI1, DI2
DO1, DO2
LDP1, LDP2
PAD
SIMPLIFIED
SYMBOL
(1)
DESCRIPTION
PCF8801
28, 27, 3, 4 V
DD
30, 29, 1, 2 V
SS
16
15
10
14
13, 17, 18
31, 173
32, 174
19
33 to 172
24, 7
23, 8
26, 5
DI
DO
LDPI, LDPO
COM1
COM2
V
DD
V
SS
Power supply for output drivers, backplane drivers and LCD
bias generator; 4 pads connected internally
Ground for output drivers, backplane drivers and LCD bias
generator; 4 pads connected internally
Power supply for remaining circuitry; connect externally to
V
DD1
to V
DD4
Ground for remaining circuitry; connect externally to
V
SS1
to V
SS4
Enable internal oscillator input; connected via an external
resistor
Reset input; active HIGH
Test pads; must remain unconnected
First pair of identical 3-level LCD backplane outputs; each
pad is located on opposite sides of the die
Second pair of identical 3-level LCD backplane outputs;
each pad is located on opposite sides of the die
Data direction control input; its voltage level determines the
direction in which data is shifted
LCD driver outputs
Data input; the status of DIR determines which pad is valid;
each pad is located on opposite sides of the die
Data outputs; both identical; both always valid; for cascade
use; each pad is located on opposite sides of the die
Data load control input (LDPI) and output (LDPO) on rising
edge; the status of DIR determines which pad is valid; each
pad is located on opposite sides of the die
Data load control input (LDNI) and output (LDNO) on falling
edge; the status of DIR determines which pad is valid; each
pad is located on opposite sides of the die
Data shift clock input (CLKI) and output (CLKO); the status
of DIR determines which pad is valid; for cascade use; each
pad is located on opposite sides of the die
LDN1, LDN2
25, 6
LDNI, LDNO
CLK1, CLK2
22, 9
CLKI, CLKO
OSC1, OSC2
21, 11
OSCI, OSCO LCD multiplexing clock input (OSCI) and output (OSCO);
the status of DIR determines which pad is valid; each pad is
located on opposite sides of the die
INT_OSCO
Internal oscillator outputs; both identical; each pad is
located on opposite sides of the die
INT_OSCO1, INT_OSCO2 20, 12
Note
1. These symbols simplify descriptions in this data sheet where several pads have the same function and also indicate
the direction of data on pads which can be selected to be either an input or an output.
2000 Feb 04
4
Philips Semiconductors
Product specification
LCD driver for 140
×
2 segments
FUNCTIONAL DESCRIPTION
Refer to block diagram Fig.1. The PCF8801 comprises a
bi-directional 280-bit input shift register, 280-bit output
register, output multiplexer providing 140-segment outputs
via a routing block and output drivers, two 3-level
backplane outputs, internal oscillator and internal
power-on reset circuit. To reduce the length of routing
required between cascaded chips in multiple chip-on-glass
applications, all inputs/outputs for control lines, clock
signals and data are provided at both sides of the narrow
package.
Shift register
The 280-bit bi-directional shift register shifts data on the
rising edge of clock signal CLKI. The shift register output
bits are called SH1_1, SH1_2 to SH140_1, SH140_2.
The direction in which data is shifted and the pads that are
valid for inputs DI, CLKI and output CLKO, is determined
by the voltage level on pad DIR. The voltage on pad DIR
must be tied to either V
DD
or V
SS
and must not be switched
when the PCF8801 is operating. The relationship between
the status of pad DIR and the other pads connected to the
shift register is shown in Table 1.
Table 1
280-bit bi-directional shift register pads
VALID PAD
SHIFT DIRECTION
DIR = 1
Data input DI
(1)
Data output DO
(2)
Clock input CLKI
Clock output CLKO
(2)
First bit shifted
Last bit shifted
(3)
Notes
1. The invalid DI pad must be connected to either V
DD
or
V
SS
.
2. Pads DO and CLKO are used when PCF8801 devices
are connected in cascade.
3. The last bit is loaded into a flip-flop whose output is
connected to pad DO. The value of the last bit appears
at pad DO delayed by a
1
⁄
2
CLKI period.
DI1
DO1 and DO2
CLK1
CLK2
SH140_2
SH1_1
DI2
DO1 and DO2
CLK2
CLK1
SH1_1
SH140_2
DIR = 0
Output register
PCF8801
The 280-data bits (SH1_1, SH1_2 to SH140_1, SH140_2)
from the output of the shift register are transferred to the
input of the 280 bit output register. Data is transferred
when either pad LDPI goes HIGH or when pad LDNI goes
LOW. The output register bits are called IO1_1, IO1_2
to IO140_1, IO140_2. The pads that are valid for
inputs LDPI, LDNI, OSCI, and outputs LDPO, LDNO,
OSCO are determined by the voltage level on pad DIR.
During a positive pulse on pad LDPI, pad LDNI must stay
HIGH, or during a negative pulse on pad LDNI, pad LDPI
must stay LOW. The voltage on pad DIR must be tied to
either V
DD
or V
SS
and must not be switched when the
PCF8801 is operating. The relationship between the
status of pad DIR and the other pads connected to the
output register is shown in Table 2.
Table 2
280-bit output register pads
VALID PAD
SHIFT DIRECTION
DIR = 1
Data load input LDPI
Data load output LDPO
Data load input LDNI
Data load output LDNO
Multiplexing clock input OSCI
Multiplexing clock output OSCO
LDP1
LDP2
LDN1
LDN2
OSC1
OSC2
DIR = 0
LDP2
LDP1
LDN2
LDN1
OSC2
OSC1
Output multiplexer, frame generator and backplane
drivers
The 280 data bits (IO1_1, IO1_2 to IO140_1, IO140_2)
from the output register are transferred to the input of the
output multiplexer which multiplexes the data at the rate of
1 : 2. The 140 output bits from the output multiplexer are
called OM1 to OM140. The frame generator outputs two
control signals derived from the LCD multiplex clock
(OSCI) called COMMON (
1
⁄
2
f
OSC
) and M (
1
⁄
4
f
OSC
) which
control the output multiplexer and the backplane drivers.
The operation of the output multiplexer is defined in
Table 3.
2000 Feb 04
5
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