PCF8563
Real-time clock/calendar
16 April 1999
Product specification
1. General description
The PCF8563 is a CMOS real-time clock/calendar optimized for low power
consumption. A programmable clock output, interrupt output and voltage-low detector
are also provided. All address and data are transferred serially via a two-line
bidirectional I
2
C-bus. Maximum bus speed is 400 kbits/s. The built-in word address
register is incremented automatically after each written or read data byte.
2. Features
s
Provides year, month, day, weekday, hours, minutes and seconds based on
32.768 kHz quartz crystal
s
Century flag
s
Wide operating supply voltage range: 1.0 to 5.5 V
s
Low back-up current; typical 0.25
µA
at V
DD
= 3.0 V and T
amb
= 25
°C
s
400 kHz two-wire I
2
C-bus interface (at V
DD
= 1.8 to 5.5 V)
s
Programmable clock output for peripheral devices: 32.768 kHz, 1024 Hz,
32 Hz and 1 Hz
s
Alarm and timer functions
s
Voltage-low detector
s
Integrated oscillator capacitor
s
Internal power-on reset
s
I
2
C-bus slave address: read A3H; write A2H
s
Open drain interrupt pin.
3. Applications
s
s
s
s
Mobile telephones
Portable instruments
Fax machines
Battery powered products.
Philips Semiconductors
PCF8563
Real-time clock/calendar
8. Functional description
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address
register, an on-chip 32.768 kHz oscillator with an integrated capacitor, a frequency
divider which provides the source clock for the Real-Time Clock (RTC), a
programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz
I
2
C-bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all
bits are implemented. The first two registers (memory address 00H and 01H) are
used as control and/or status registers. The memory addresses 02H through 08H are
used as counters for the clock function (seconds up to year counters). Address
locations 09H through 0CH contain alarm registers which define the conditions for an
alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the
timer control and timer registers, respectively.
The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute alarm,
Hour alarm and Day alarm registers are all coded in BCD format. The Weekdays and
Weekday alarm register are not coded in BCD format.
When one of the RTC registers is read the contents of all counters are frozen.
Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
8.1 Alarm function modes
By clearing the MSB (bit AE = Alarm Enable) of one or more of the alarm registers,
the corresponding alarm condition(s) will be active. In this way an alarm can be
generated from once per minute up to once per week. The alarm condition sets the
alarm flag, AF (bit 3 of Control/Status 2 register). The asserted AF can be used to
generate an interrupt (INT). Bit AF can only be cleared by software.
8.2 Timer
The 8-bit countdown timer (address 0FH) is controlled by the Timer Control register
(address 0EH; see
Table 25).
The Timer Control register selects one of 4 source
clock frequencies for the timer (4096, 64, 1, or
1
⁄
60
Hz), and enables/disables the
timer. The timer counts down from a software-loaded 8-bit binary value. At the end of
every countdown, the timer sets the timer flag TF (see
Table 7).
The timer flag TF can
only be cleared by software. The asserted timer flag TF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of TF. TI/TP (see
Table 7)
is used to control this mode selection. When reading the timer, the current
countdown value is returned.
8.3 CLKOUT output
A programmable square wave is available at the CLKOUT pin. Operation is controlled
by the CLKOUT frequency register (address 0DH; see
Table 23).
Frequencies of
32.768 kHz (default), 1024, 32 and 1 Hz can be generated for use as a system clock,
microcontroller clock, input to a charge pump, or for calibration of the oscillator.
CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes
high-impedance.
9397 750 04855
© Philips Electronics N.V. 1999. All rights reserved.
Product specification
16 April 1999
4 of 30
Philips Semiconductors
PCF8563
Real-time clock/calendar
8.4 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator
is stopped. In the reset state the I
2
C-bus logic is initialized and all registers, including
the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC
and AE which are set to logic 1.
8.5 Voltage-low detector and clock monitor
The PCF8563 has an on-chip voltage-low detector. When V
DD
drops below V
low
the
VL bit (Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable
clock/calendar information is no longer guaranteed. The VL flag can only be cleared
by software.
The VL bit is intended to detect the situation when V
DD
is decreasing slowly for
example under battery operation. Should V
DD
reach V
low
before power is re-asserted
then the VL bit will be set. This will indicate that the time may be corrupted.
handbook, halfpage
MGR887
VDD
normal power
operation
period of battery
operation
Vlow
t
VL set
Fig 4. Voltage-low detection.
8.6 Register organization
Table 4: Registers overview
Bit positions labelled as ‘
−
’are not implemented; those labelled with ‘0’ should always be written with logic 0.
Address Register name
00H
01H
0DH
0EH
0FH
Control/Status 1
Control/Status 2
CLKOUT frequency
Timer control
Timer countdown
value
Bit 7
TEST1
0
FE
TE
Bit 6
0
0
−
−
Bit 5
STOP
0
−
−
Bit 4
0
TI/TP
−
−
Bit 3
TESTC
AF
−
−
Bit 2
0
TF
−
−
Bit 1
0
AIE
FD1
TD1
Bit 0
0
TIE
FD0
TD0
<timer countdown value>
9397 750 04855
© Philips Electronics N.V. 1999. All rights reserved.
Product specification
16 April 1999
5 of 30
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