INTEGRATED CIRCUITS
DATA SHEET
PCF8549
65
×
102 pixels matrix LCD driver
Product specification
File under Integrated Circuits, IC12
1997 Nov 21
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
FEATURES
•
Single chip LCD controller/driver
•
65 row and 102 column outputs
•
Display data RAM 65
×
102 bits
•
On-chip:
– Generation of LCD supply voltage
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components (external
clock also possible)
•
400 kHz Fast I
2
C Interface
•
CMOS compatible inputs
•
Mux rate: 65
•
Logic supply voltage range V
DD1
−
V
SS
: 1.5 to 6 V
•
Voltage generator voltage range V
DD2/2_HV
−
V
SS
:
2.4 to 5 V
•
Display supply voltage range V
LCD
−
V
SS
: 7.0 to 16 V
•
Low power consumption, suitable for battery operated
systems
•
Temperature compensation of V
LCD
•
Interlacing for better display quality
•
Slim chip layout, suited for chip-on-glass applications.
APPLICATIONS
•
Telecom equipment
•
Portable instruments
•
Point of sale terminals.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8549U/2/F1
TRAY
chip with bumps in tray
DESCRIPTION
GENERAL DESCRIPTION
PCF8549
The PCF8549 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 65 rows and
102 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption. The
PCF8549 interfaces to most microcontrollers via an
I
2
C interface.
Packages
The PCF8549U/2 is available as bumped die. Sawn wafer
as chip sorted in chip tray. For further details see
Section “Bonding pads”.
Customized TCP upon request.
VERSION
1997 Nov 21
2
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
BLOCK DIAGRAM
PCF8549
C0 to C101
R0 to R64
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES
VLCD2
Bias vol-
tage gene-
rator
SHIFT REGISTER
OSCILLATOR
VLCD1
HVGEN
7 stages
Dual Ported RAM
65x102 Bit
TIMING GENERATOR
OSC
IIC INTERFACE
DISPLAY CONTROL LOGIC
Fig.1 Block diagram.
1997 Nov 21
3
VDD1
VDD2
VDD2_HV
VSS1
VSS2
VSS2_HV
SDA_out
SDA
SCL
RES
SA0
T1
T2
T3
T4
T5
T6
T7
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PINNING
SYMBOL
R0 to R64
C0 to C101
V
SS1,2,2_HV
V
DD1,2,2_HV
V
LCD1,2
T1
T2
T3
T4
T5
T6
T7
SDA
SCL
SDA_OUT
SA0
OSC
RES
Pin functions
R0
TO
R64:
ROW DRIVER OUTPUTS
These pads output the row signals.
C0
TO
C101:
COLUMN DRIVER OUTPUTS
These pads output the column signals.
V
SS1,2,2_HV
:
NEGATIVE POWER SUPPLY RAILS
Negative power supplies.
V
DD1,2,2_HV
:
POSITIVE POWER SUPPLY RAILS
DESCRIPTION
LCD row driver outputs
LCD column driver outputs
negative power supply
supply voltage
LCD supply voltage
test 1 input
test 2 output
test 3 I/O
test 4 I/O
test 5 input
test 6 input
test 7 input
I
2
C data input
I
2
C clock line
I
2
C output
least significant bit of slave address
oscillator
external reset input, low active
PCF8549
V
DD2
and V
DD2_HV
are the supply voltages for the internal voltage generator. Both have to be on the same voltage and
may be connected together outside of the chip. If the internal voltage generator is not used, they should be both
connected to ground. V
DD1
is used as power supply for the rest of the chip. This voltage can be a different voltage than
V
DD2
and V
DD2_HV
.
V
LCD1,2
: LCD
POWER SUPPLY
Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails
V
LCD1
and V
LCD2
must be connected together. An external LCD supply voltage can be supplied using the V pad. In this
case, V
LCD1
has to be connected to ground, and the internal voltage generator has to be programmed to zero. If the
PCF8549 is in power-down mode, the external LCD supply voltage has to be switched off.
1997 Nov 21
4
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
T1, T2, T3, T4, T5, T6
AND
T7:
TEST PADS
T1, T3, T4, T5, T6 and T7 must be connected to V
SS1
, T2
is to be left open. Not accessible to user.
SDA/SDA_OUT: I
2
C D
ATA LINES
Output and input are separated. If both pads are
connected together they behave like a standard I
2
C pad.
SCL: I
2
C
CLOCK SIGNAL
Input for the I
2
C-bus clock signal.
SA0: S
LAVE ADDRESS
With the SA0 pin two different slave addresses can be
selected. That allows to connect two PCF8549 LCD
drivers to the same I
2
C-bus.
OSC:
OSCILLATOR
When the on-chip oscillator is used this input must be
connected to V
DD1
. An external clock signal, if used, is
connected to this input.
RES:
RESET
This signal will reset the device. Signal is active low.
FUNCTIONAL DESCRIPTION
Block diagram functions
O
SCILLATOR
PCF8549
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
DD1
. An external
clock signal, if used, is connected to this input.
I
2
C I
NTERFACE
The I
2
C interface receives and executes the commands
sent via the I
2
C-bus. It also receives RAM-data and sends
them to the RAM. During read access the 8-bit parallel
data or the status register content is converted to a serial
data stream and output via the I
2
C-bus.
D
ISPLAY CONTROL LOGIC
The display control logic generates the control signals to
read out the RAM via the 101 bit parallel port. It also
generates the control signals for the row, and
column drivers.
D
ISPLAY DATA
RAM (DDRAM)
The PCF8549 contains a 65
×
102 bit static RAM which
stores the display data. The RAM is divided into 8 banks of
102 bytes and one bank of 102 bits
((8
×
8 + 1)
×
102 bits). During RAM access, data is
transferred to the RAM via the I
2
C interface. There is a
direct correspondence between X-address and column
output number.
T
IMING GENERATOR
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I
2
C-bus.
LCD
ROW AND COLUMN DRIVERS
The PCF8549 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2 shows typical waveforms. Unused outputs should
be left unconnected.
1997 Nov 21
5
FPGA/CPLD
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