Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
CONTENTS
1
2
3
3.1
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
8.1
8.2
8.3
8.4
8.5
8.6
9
10
10.1
10.2
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
Packages
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
PIN FUNCTIONS
R0 to R64: row driver outputs
C0 to C101: column driver outputs
V
SS1
and V
SS2
: negative power supply rails
V
DD1
to V
DD3
: positive power supply rails
V
LCDIN
: LCD power supply
V
LCDOUT
: LCD power supply
V
LCDSENSE
: voltage multiplier regulation input
(V
LCD
)
T1 to T12: test pads
SDAIN and SDAOUT: I
2
C-bus data lines
SCL: I
2
C-bus clock signal
SA0: slave address
OSC: oscillator
RES: reset
BLOCK DIAGRAM FUNCTIONS
Oscillator
I
2
C-bus interface
Display control logic
Display Data RAM (DDRAM)
Timing generator
LCD row and column drivers
INITIALIZATION
ADDRESSING
Display data RAM structure
RAM access
I
2
C-BUS INTERFACE
Characteristics of the I
2
C-bus
Bit transfer
START and STOP conditions
System configuration
Acknowledge
I
2
C-bus protocol
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.3
12.3.1
12.4
12.4.1
12.4.2
12.5
12.6
12.7
12.7.1
12.8
12.9
12.10
13
14
15
16
17
18
19
20
21
22
23
24
25
26
INSTRUCTIONS
External reset (RES)
Function set
Power-Down (PD)
V
H
MX
MY
Display control
D and E
Display configuration
TRS
BRS
Set Y address of RAM
Set X address of RAM
Set HV generator stages
S[1:0]
Temperature control
Bias system
Set V
OP
value
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
RESET
PCF8548
APPLICATION INFORMATION
CHIP INFORMATION
PAD INFORMATION
DEVICE PROTECTION DIAGRAM
TRAY INFORMATION
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
BARE DIE DISCLAIMER
1999 Aug 16
2
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
1
FEATURES
PCF8548
•
Single-chip LCD controller/driver
•
65 row and 102 column outputs
•
Display data RAM 65
×
102 bits
•
On-chip:
– Configurable 5 (4, 3 and 2)
×
voltage multiplier
generating V
LCD
(external V
LCD
also possible)
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components
(external clock also possible).
•
400 kbits/s fast I
2
C-bus interface
•
CMOS compatible inputs
•
Mux rate: 1 : 65
•
Logic supply voltage range V
DD1
to V
SS
:
– 1.9 to 5.5 V.
•
High voltage generator supply voltage range V
DD2
to
V
SS
and V
DD3
to V
SS
:
– 2.4 to 4.5 V with LCD voltage internally generated
(voltage generator enabled).
•
Display supply voltage range V
LCD
to V
SS
:
– 4.5 to 9.0 V
•
Low power consumption, suitable for battery operated
systems
•
Temperature compensation of V
LCD
•
Slim chip layout, suitable for Chip-On-Glass (COG)
applications
•
Programmable bottom row pads mirroring and top row
pads mirroring, for compatibility with both Tape Carrier
Package (TCP) and COG applications.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8548U/2
PCF8548U/9
Tray
Bumped wafer
chip with bumps in tray
quarter wafer
DESCRIPTION
VERSION
−
−
2
APPLICATIONS
•
Telecom equipment
•
Portable instruments
•
Point of sale terminals.
3
GENERAL DESCRIPTION
The PCF8548 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 65 rows and
102 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption.
The PCF8548 interfaces to most microcontrollers via an
I
2
C-bus interface.
3.1
Packages
The PCF8548 is available as chip with bumps in tray; tape
carrier package is available on request.
1999 Aug 16
3
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
7
7.1
PIN FUNCTIONS
R0 to R64: row driver outputs
7.8
T1 to T12: test pads
PCF8548
These pads output the row signals.
7.2
C0 to C101: column driver outputs
T1 and T3 to T7 must be connected to V
SS1
. T8 must be
connected to V
DD1
. T2 and T9 to T12 must be left
open-circuit; not accessible to user.
7.9
SDAIN and SDAOUT: I
2
C-bus data lines
These pads output the column signals.
7.3
V
SS1
and V
SS2
: negative power supply rails
V
SS2
is related to V
DD2
and V
DD3
and V
SS1
is related to
V
DD1
.
7.4
V
DD1
to V
DD3
: positive power supply rails
V
DD2
and V
DD3
are the supply voltages for the internal
voltage generator. Both have to be at the same voltage
and must be connected together outside of the chip. If the
internal voltage generator is not used, they should both be
connected to power or to the V
DD1
pad.
V
DD1
is used as the power supply for the rest of the chip.
This voltage can be a different voltage than V
DD2
and
V
DD3
.
7.5
V
LCDIN
: LCD power supply
Serial data and acknowledge lines for the I
2
C-bus.
By connecting SDAIN to SDAOUT, the SDA line becomes
fully I
2
C-bus compatible. Having the acknowledge output
(SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8548
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid
LOW level.
7.10
SCL: I
2
C-bus clock signal
Internally generated positive power supply for the liquid
crystal display. An external LCD supply voltage can be
supplied using the V
LCDIN
pad. In this case, V
LCDOUT
has
to be connected to ground, and the internal voltage
generator has to be programmed to zero. If the PCF8548
is in power-down mode, the external LCD supply voltage
must be switched off.
7.6
V
LCDOUT
: LCD power supply
I
2
C-bus serial clock signal input.
7.11
SA0: slave address
Two different slave addresses can be selected using the
SA0 pad. This allows two PCF8548 LCD drivers to be
connected to the same I
2
C-bus.
7.12
OSC: oscillator
Positive power supply for the liquid crystal display. If the
internal voltage generator is used, the two supply rails
V
LCDIN
and V
LCDOUT
must be connected together and an
external capacitor must be connected (see Fig.19).
7.7
V
LCDSENSE
: voltage multiplier regulation input
(V
LCD
)
When the on-chip oscillator is used this input must be
connected to V
DD1
. An external clock signal, if used, is
connected to this input.
7.13
RES: reset
This signal is used to reset the device. The signal is active
LOW.
V
LCDSENSE
is the input voltage for the internal voltage
multiplier regulation.
If the internal voltage generator is used then V
LCDSENSE
must be connected to V
LCDOUT
. If an external supply
voltage is used then V
LCDSENSE
must be connected to
ground.
1999 Aug 16
5
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