INTEGRATED CIRCUITS
DATA SHEET
PCF8535
65
×
133 pixel matrix driver
Objective specification
File under Integrated Circuits, IC12
1999 Aug 24
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
CONTENTS
1
2
3
4
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
Block diagram functions
Oscillator
Power-on reset
I
2
C-bus controller
Input filters
Display data RAM
Timing generator
Address counter
Display address counter
PINNING
Pin functions
R0 to R64
C0 to C132
V
SS1
and V
SS2
V
DD1
to V
DD3
V
LCDOUT
V
LCDIN
V
LCDSENSE
SDA
SDAOUT
SCL
SA0 and SA1
OSC
RES
T1, T2, T3, T4 and T5
FUNCTIONAL DESCRIPTION
Reset
Power-down
LCD voltage selector
Oscillator
Timing
Column driver outputs
Row driver outputs
Drive waveforms
Set multiplex rate
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
7.13.1
7.14
7.14.1
7.15
7.15.1
7.15.2
7.16
7.16.1
7.16.2
7.16.3
7.16.4
7.16.5
7.16.6
7.17
7.17.1
7.17.2
8
9
10
11
12
13
14
15
16
17
18
19
20
PCF8535
Bias system
Set bias system
Temperature measurement
Temperature read back
Temperature compensation
Temperature coefficients
V
OP
Set V
OP
value
Voltage multiplier control
S[1:0]
Addressing
Input addressing
Output addressing
Instruction set
RAM read/write command page
Function and RAM command page
Display setting command page
HV-gen command page
Special feature command page
Instruction set
I
2
C-bus interface
Characteristics of the I
2
C-bus
I
2
C-bus protocol
LIMITING VALUES (PROVISIONAL)
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
RESET TIMING
APPLICATION INFORMATION
BONDING PAD LOCATIONS
DEVICE PROTECTION DIAGRAM
TRAY INFORMATION
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
BARE DIE DISCLAIMER
1999 Aug 24
2
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
1
FEATURES
PCF8535
•
Single-chip LCD controller/driver
•
65 row, 133 column outputs
•
Display data RAM 65
×
133 bits
•
133 icons (last row is used for icons)
•
Fast mode I
2
C-bus interface (400 kbits/s)
•
Software selectable multiplex rates:
1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65
•
On-chip:
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components
(external clock also possible)
– Generation of V
LCD
.
•
CMOS compatible inputs
•
Software selectable bias configuration
•
Logic supply voltage range V
DD1
to V
SS1
4.5 to 5.5 V
•
Supply voltage range for high voltage part V
DD2
and
V
DD3
to V
SS2
and V
SS3
4.5 to 5.5 V
•
Display supply voltage range V
LCD
to V
SS
:
– Mux rate 1 : 65: 8 to 16 V.
•
Low power consumption, suitable for battery operated
systems
•
Internal Power-on reset and/or external reset
•
Temperature read back available
•
Manufactured in N-well silicon gate CMOS process.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8535U
−
DESCRIPTION
chip with bumps in tray
VERSION
−
2
APPLICATIONS
•
Automotive information systems
•
Telecommunication systems
•
Point-of-sale terminals
•
Instrumentation.
3
GENERAL DESCRIPTION
The PCF8535 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65.
Furthermore, it can drive up to 133 icons. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages,
resulting in a minimum of external components and low
power consumption. The PCF8535 is compatible with
most microcontrollers and communicates via an industry
standard two-line bidirectional I
2
C-bus serial interface.
All inputs are CMOS compatible.
1999 Aug 24
3
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
5
BLOCK DIAGRAM
PCF8535
handbook, full pagewidth
R0 to R64
C0 to C132
VDD1
VDD2
VDD3
65
VSS1
VSS2
T4, T5
T1, T2, T3
ROW
DRIVERS
133
COLUMN
DRIVERS
POWER-ON RESET
PCF8535
INTERNAL
RESET
RES
DATA LATCHES
VLCDIN
BIAS
VOLTAGE
GENERATOR
MATRIX
LATCHES
OSCILLATOR
OSC
TIMING
GENERATOR
DISPLAY DATA RAM
VLCD
GENERATOR
MATRIX DATA
RAM
DISPLAY
ADDRESS
COUNTER
VLCDSENSE
VLCDOUT
SCL
SDA
SDAOUT
INPUT
FILTERS
I
2
C-BUS
CONTROL
COMMAND
DECODER
ADDRESS
COUNTER
MGS669
SA1
SA0
Fig.1 Block diagram.
1999 Aug 24
4
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
5.1
5.1.1
Block diagram functions
O
SCILLATOR
5.1.5
D
ISPLAY DATA
RAM
PCF8535
The on-chip oscillator provides the display clock for the
system; it requires no external components. Alternatively,
an external display clock may be provided via the OSC
input. The OSC input must be connected to V
DD1
or V
SS1
when not in use. During power-down additional current
saving can be made if the external clock is disabled.
5.1.2
P
OWER
-
ON RESET
The PCF8535 contains a 65
×
133 bit static RAM which
stores the display data. The RAM is divided into 9 banks of
133 bytes. The last bank is used for icon data and is only
one bit deep. During RAM access, data is transferred to
the RAM via the I
2
C-bus interface. There is a direct
correspondence between the X address and the column
output number.
5.1.6
T
IMING GENERATOR
The on-chip Power-on reset initializes the chip after
power-on or power failure.
5.1.3
I
2
C-
BUS CONTROLLER
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data bus.
5.1.7
A
DDRESS COUNTER
The I
2
C-bus controller detects the I
2
C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel).
The PCF8535 acts as an I
2
C-bus slave and therefore
cannot initiate bus communication.
5.1.4
I
NPUT FILTERS
The Address Counter (AC) sends addresses to the Display
Data RAM (DDRAM) for writing.
5.1.8
D
ISPLAY ADDRESS COUNTER
Input filters are provided to enhance noise immunity in
electrically adverse environments; RC low-pass filters are
provided on the SDA, SCL and RES lines.
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on or off, normal or inverse
video) is set via the I
2
C-bus.
1999 Aug 24
5
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