INTEGRATED CIRCUITS
DATA SHEET
PCF84C21A; PCF84C41A;
PCF84C81A
Telecom microcontrollers
Product specification
Supersedes data of 1995 Jul 14
File under Integrated Circuits, IC14
1996 Nov 20
Philips Semiconductors
Product specification
Telecom microcontrollers
CONTENTS
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
14.1
14.2
14.2.1
14.2.2
14.3
14.3.1
14.3.2
14.3.3
15
16
17
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
Pinning
Pin description
INSTRUCTION SET
HIGH SINK OUTPUT CURRENTS
ROM MASK OPTIONS
HANDLING
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
Introduction
DIP
Soldering by dipping or by wave
Repairing soldered joints
SO
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
PCF84C21A; PCF84C41A;
PCF84C81A
1996 Nov 20
2
Philips Semiconductors
Product specification
Telecom microcontrollers
1
FEATURES
2
PCF84C21A; PCF84C41A;
PCF84C81A
GENERAL DESCRIPTION
•
Manufactured in silicon gate CMOS process
•
8-bit CPU, ROM, RAM, I/O in a 28-lead package
•
2 kbyte ROM, 64 byte RAM (PCF84C21A)
•
4 kbyte ROM, 128 byte RAM (PCF84C41A)
•
8 kbyte ROM, 256 byte RAM (PCF84C81A)
•
I
2
C-bus interface with multi-master capability
•
Over 100 instructions (based on MAB8048) all of
1 or 2 cycles
•
20 quasi-bidirectional I/O Port lines
•
High sink current capability on the 8 lines of Port 1
•
8-bit programmable timer/event counter 1
•
3 single-level vectored interrupts:
– external
– 8-bit programmable timer/event counter 1
– I
2
C-bus
•
Two test inputs, one of which also serves as the external
interrupt input
•
Stop and Idle modes
•
Supply voltage: 2.5 to 5.5 V
•
Clock frequency: 1 to 16 MHz
•
Operating temperature:
−40
to +85
°C.
3
ORDERING INFORMATION
(see note 1)
This data sheet details the specific properties of the
PCF84C21A, PCF84C41A and PCF84C81A. The shared
properties of the PCF84CxxxA family of microcontrollers
are described in the
“PCF84CxxxA family”
data sheet
which should be read in conjunction with this publication.
The PCF84C21A, PCF84C41A and PCF84C81A are
general purpose CMOS microcontrollers with 2 kbytes,
4 kbytes and 8 kbytes of program memory and 64,128 and
256 bytes of RAM, respectively. In addition to 20 I/O port
lines, the microcontrollers provide an on-chip I
2
C-bus
interface. This two-line serial bus extends the
microcontroller capabilities when implemented with the
powerful I
2
C-bus peripherals. These include LCD drivers,
I/O expanders, telecom circuits, ADC and DAC converters,
clock/calendar circuits, EEPROM and RAM and are listed
in
“Data Handbook IC12, I
2
C Peripherals”.
The instruction set is based on that of the MAB8048 and
is a sub-set of that listed in the
“PCF84CxxxA family”
data
sheet.
PACKAGE
TYPE NUMBER
NAME
PCF84C21AP
PCF84C41AP
PCF84C81AP
PCF84C21AT
PCF84C41AT
PCF84C81AT
Note
1. Please refer to the Order Entry Form (OEF) for these devices for the full type number to use when ordering. This type
number will also specify the required program and the ROM mask options.
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
DIP28
DESCRIPTION
plastic dual in-line package; 28 leads (600 mil)
VERSION
SOT117-1
1996 Nov 20
3
4
P2.0 to P2.2
8
PORT 1
BUFFER
PORT 0
BUFFER
PORT 0
FLIP-FLOPS
PORT 1
FLIP-FLOPS
8
P1.0 to P1.7
P0.0 to P0.7
SCLK
handbook, full pagewidth
1996 Nov 20
BLOCK DIAGRAM
RESIDENT ROM
2 kbytes
(PCF84C21A)
4 kbytes
(PCF84C41A)
8 kbytes
(PCF84C81A)
DECODE
INTERNAL
CLOCK
FREQ.
30
MEMORY
BANK
FLIP-FLOPS
32
T1
8
8
5
8
8
8
TIMER/
EVENT
COUNTER
PROGRAM
STATUS
WORD
HIGHER
PROGRAM
COUNTER
LOWER
PROGRAM
COUNTER
SDA/P2.3
3
CLOCK
DATA
PORT 2
BUFFER
Philips Semiconductors
Telecom microcontrollers
PORT 2
FLIP-FLOPS
I
2
C-BUS
INTERFACE
8
4
8
8
8
8
8
8
8
MULTIPLEXER
4
TEMPORARY
REGISTER 2
TEMPORARY
REGISTER 1
ARITHMETIC
LOGIC UNIT
INSTRUCTION
REGISTER
&
DECODER
T1
DECIMAL
ADJUST
TIMER
FLAG
CONDITIONAL
BRANCH
LOGIC
CARRY
ACC
XTAL 2
INT / T0
INITIALIZE
CONTROL &
TIMING
RESET
XTAL 1
OSCILLATOR
INTERRUPT
LOGIC
ACCUMULATOR
timer interrupt
SIO/
derivative
interrupt
RAM
ADDRESS
REGISTER
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
INT / T0
D
E
C
O
D
E
8 LEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK
external interrupt
DATA STORE
STOP
IDLE
ACC BIT
TEST
INTERRUPT
MBB561 - 1
RESIDENT RAM ARRAY
64 bytes
(PCF84C21A)
128 bytes
(PCF84C41A)
256 bytes
(PCF84C81A)
PCF84C21A; PCF84C41A;
PCF84C81A
Product specification
Fig.0 Block diagram of PCF84C21A, PCF84C41A and PCF84C81A.
Fig.1 Block diagram of PCF84C21A; PCF84C41A and PCF84C81A.
Philips Semiconductors
Product specification
Telecom microcontrollers
5
5.1
PINNING INFORMATION
Pinning
5.2
PCF84C21A; PCF84C41A;
PCF84C81A
Pin description
DIP28 and SO28 packages
PIN
1
2
FUNCTION
1 bit of Port 2: 4-bit
quasi-bidirectional I/O port
bidirectional data line of the
I
2
C-bus interface, or 1 bit of
Port 2: 4-bit quasi-bidirectional
I/O port
bidirectional clock line of the
I
2
C-bus interface
8 bits of Port 0: 8-bit
quasi-bidirectional I/O port
Interrupt/Test 0
Test 1/count input of 8-bit
timer/event counter 1
ground
crystal oscillator input or
external clock input
crystal oscillator output
Reset input
Table 1
SYMBOL
P2.2
P2.2
SDA/P2.3
SCLK
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
1
2
3
4
5
6
7
8
9
PCF84C21A
PCF84C41A
PCF84C81A
28
V DD
SDA/P2.3
27 P2.1
26 P2.0
25 P1.7
SCLK
24 P1.6
23 P1.5
22 P1.4
21 P1.3
20 P1.2
19 P1.1
18 P1.0
17 RESET
3
P0.0 to P0.7 4 to 11
INT/T0
T1
12
13
14
15
16
17
P0.6 10
P0.7
11
V
SS
XTAL1
XTAL2
INT/T0 12
T1 13
VSS
14
MBB562
16 XTAL2
15 XTAL1
RESET
P1.0 to P1.7 18 to 25 8 bits of Port 1: 8-bit
quasi-bidirectional I/O port
P2.0 to P2.1 26 to 27 2 bits of Port 2: 4-bit
quasi-bidirectional I/O port
V
DD
28
positive supply
Fig.2 Pin configuration.
6
INSTRUCTION SET
7
HIGH SINK OUTPUT CURRENTS
ROM is restricted to 2 kbytes for the PCF84C21A and
4 kbytes for the PCF84C41A. Therefore, the instructions
SEL MB1/2/3 for the PCF84C21A, and the instructions
SEL MB2/3 for the PCF84C41A should be avoided, as
they would define non-existing program memory banks.
As RAM is limited to 64 bytes for the PCF84C21A and to
128 bytes for the PCF84C41A, care should be taken to
avoid accesses to non-existing RAM locations.
See the “PCF84CxxxA
family
” data sheet for a complete
description of the instruction set.
The Port 1 outputs of these devices are designed for high
current drive in the logic 0 state. They are capable of
driving 10 mA loads and higher. Applications include drive
for small relays and light-emitting diodes (LEDs).
To avoid overload, care should be taken that the total
Port 1 current averages less than 80 mA, i.e. an average
of 10 mA per Port 1 line. Refer to Chapter “Limiting values”
which specifies an upper limit of 100 mA for I
SS
.
1996 Nov 20
5
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