Philips Semiconductors
Objective specification
GSM signal processing IC
CONTENTS
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.6
8.6.1
8.6.2
8.7
8.8
8.8.1
9
9.1
9.1.1
9.1.2
FEATURES
GENERAL DESCRIPTION
APPLICATIONS
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
Pinning
Pinning description
OVERVIEW OF THE GSM CHIP SET
General
The role of the PCF5083
FUNCTIONAL DESCRIPTION TIMER CORE
Clock generator
ON/OFF Logic
Mobile switch-on procedure
Mobile switch-off procedure
OFF/Watchdog Timer
Timing Generator
The Quarterbit Counter
Normal Mode
Sleep Mode
RF-IC Interface Bus
Frequency Setting Channel
Gain Control Channel
Immediate Control Channel
Operation Modes and Control Registers
IOM
®
-2 Interface
IOM
®
-2 Clock Generation
IOM
®
-2 Master Unit
Monitor Channel Transmitter Protocol
Monitor Channel Receiver Protocol
Command/Indication Channel Transmitter
Command/Indication Channel Receiver
Audio Interface
External IOM
®
-2 Interface
MMI Interface
RS232 Interface
MMI power-down Interface
General purpose parallel I/O-port
Real Time Clock
Setting the real time clock
DESCRIPTION OF THE DSP CORE
Interface description
Baseband Digitizer Interface
GMSK Modulator Interface
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.4.3
9.4.4
10
10.1
10.2
11
12
13
14
15
16
17
18
19
19.1
19.2
19.3
19.4
20
21
PCF5083
Audio and Data Interface
Audio interface
Terminal adaptor interface for data services
System controller interface
Event Counter Clock
Usage of General Purpose I/O Pins
Power saving modes
Message Interface to the System Controller
Execution of GSM baseband procedures
No Operation (NOP) command
Soft resetting the DSP
Error handling
GSM baseband procedures
Procedure description
Performance of GSM baseband procedures
Software applications
Receiving a CCH block
Transmitting a CCH block
FB search for timing synchronization
Processing a TCH/FS multiframe
MICROCONTROLLER INTERFACE
Register Set for the Timer Core
Interrupt Logic
RESET
JTAG TEST INTERFACE
TEST AND EMULATION MODES
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1996 Oct 29
2
Philips Semiconductors
Objective specification
GSM signal processing IC
1
FEATURES
PCF5083
– RS232 interface for the man machine interface
controller
– Man machine interface power-down control
– Power supply control logic with Watchdog Timer
– Real time clock and calendar running on 32.768 kHz
– 6-bit general purpose I/O port
•
Reduced swing 13 MHz main clock input
•
On-chip PLL to derive the DSP and microcontroller clock
•
8-bit, 68000 compatible host interface with three
interrupt lines
•
Boundary scan interface in accordance with
“IEEE Standard 1149.1-1990”.
2
GENERAL DESCRIPTION
•
Fabricated in a 0.5
µm
CMOS process with 3-layer
metal
•
LQFP128 package (SOT420AA-2)
•
3.3 V operation
•
Low power
•
Embedded DSP core for all GSM specific signal
processing tasks:
– 16-bit fixed point DSP
– 19.5 MHz or external clock operation
– Flexible power-down modes
– 5 kbyte on-chip program or data RAM
– 2 kbyte on-chip data ROM
– 16 kbyte on-chip program ROM
– Fully pre-programmed modules for GSM baseband
tasks including all data channels
– Dedicated GSM signal processor with application
specific hardware for: equalisation, channel
encoding/decoding for all traffic and control channels
and encryption/decryption (A5/1 and A5/2
algorithms)
– Tone and side-tone generation
•
GSM Hardware Timer and Interface core:
– Power saving Sleep mode for GSM mobiles
– Programmable TDMA timing and power-down
signals with 0.25 bit resolution
– Three wire serial control bus for fast programming of
RF ICs and synthesizers
– IOM
®
-2 interface for external accessories, host
software download and support of the Digital Audio
Interface (DAI)
4
ORDERING INFORMATION
3
The PCF5083 GSM Signal Processing IC is a dedicated
VLSI circuit; fabricated in a 0.5
µm
CMOS process. It has
been designed for baseband signal processing tasks for
the Pan European Global System for Mobile
telecommunication (GSM). The PCF5083 is part of the
second generation Philips Semiconductors GSM chip set.
The PCF5083 consists of an embedded 16-bit DSP core
for all GSM specific signal processing tasks and a Timer
and Interface core which contains many peripheral
functions to simplify the system design.
APPLICATIONS
The PCF5083 is suitable for use in GSM mobile stations or
hand-helds.
PACKAGE
TYPE NUMBER
NAME
PCF5083H/F2
PCF5083H/001/F2
PCF5083H/5V2/F3
LQFP128
LQFP128
LQFP128
DESCRIPTION
plastic low profile quad flat package; 128 leads; (PCF5083-2B)
plastic low profile quad flat package; 128 leads; (PCF5083-2C)
plastic low profile quad flat package; 128 leads; (PCF5083-3A)
VERSION
SOT420-1
SOT420-1
SOT420-1
1996 Oct 29
3
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