SIT9045AI-22-28SMA150.000000E datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> SIT9045AI-22-28SMA150.000000E

SIT9045AI-22-28SMA150.000000E: DescriptionLVCMOS Output Clock Oscillator, 150MHz Nom, PQFN, 4 PIN; CategoryPassive components oscillator; File Size789KB，13 Pages; ManufacturerSiTime; Environmental Compliance

Download Datasheet Parametric View All

SIT9045AI-22-28SMA150.000000E Overview

LVCMOS Output Clock Oscillator, 150MHz Nom, PQFN, 4 PIN

SIT9045AI-22-28SMA150.000000E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145211794086
package instruction	PQFN, 4 PIN
Reach Compliance Code	unknown
Country Of Origin	Malaysia, Taiwan, Thailand
YTEOL	7.21
Other features	STANDBY; ENABLE/DISABLE FUNCTION
maximum descent time	2 ns
Frequency Adjustment - Mechanical	NO
frequency stability	25%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	4
Nominal operating frequency	150 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVCMOS
Output load	15 pF
Maximum output low current	3 mA
Encapsulate equivalent code	DILCC4,.1,83
physical size	3.2mm x 2.5mm x 0.85mm
longest rise time	2 ns
Filter level	AEC-Q100
Maximum supply voltage	3.08 V
Minimum supply voltage	2.52 V
Nominal supply voltage	2.8 V
surface mount	YES
maximum symmetry	57/43 %
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)

SIT9045AI-22-28SMA150.000000E Preview

SiT9045

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Features

◼

Applications

◼

Best acceleration sensitivity of 0.1 ppb/g

Spread spectrum for EMI reduction

▪

Wide spread % option



Center spread: from ±0.125% to ±2%, ±0.125% step size



Down spread: -0.25% to -4% with -0.25% step size

▪

Spread profile option: Triangular, Hershey-kiss, Random

Programmable rise/fall time for EMI reduction: 8 options,

0.25 to 40 ns

Extended temperature range (-55°C to 125°C)

Any frequency between 1 MHz and 150 MHz accurate to

6 decimal places

100% pin-to-pin drop-in replacement to quartz-based XO’s

Excellent total frequency stability as low as ±25 ppm

Low power consumption of 6.6 mA typical at 1.8V

Pin1 modes: Standby, output enable, or spread disable

LVCMOS output

Industry-standard packages

▪

QFN: 2.0 x 1.6 mm

, 2.5 x 2.0 mm

, 3.2 x 2.5 mm

RoHS and REACH compliant, Pb-free, Halogen-free and

Antimony-free

Avionics systems

Field communication systems

Telemetry applications

Electrical Specifications

Table 1. Electrical Characteristics

All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise

stated. Typical values are at 25°C and 3.3V supply voltage.

Parameters

Symbol

Min.

Typ.

–

Max.

Unit

Condition

Frequency Range

Output Frequency Range

150

MHz

Frequency Stability and Aging

Frequency Stability

[1]

F_stab

-25

-50

+25

+50

ppm

Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and

variations over operating temperature, rated power supply voltage.

Spread = Off.

Operating Temperature Range

Operating Temperature

Range

T_use

-40

-55

–

+85

+105

+125

°C

AEC-Q100 Grade 3

AEC-Q100 Grade 2

AEC-Q100 Grade 1

Extended cold AEC-Q100 Grade 1

Supply Voltage and Current Consumption

Supply Voltage

Vdd

1.62

2.25

2.52

2.7

2.97

2.25

Current Consumption

Idd

–

OE Disable Current

I_OD

–

Standby Current

I_std

–

1.8

2.5

2.8

3.0

3.3

–

7.9

6.6

5.3

5.0

2.6

0.6

1.98

2.75

3.08

3.3

3.63

9.5

8.0

6.5

6.0

9.0

5.0

A

No load condition, f = 148.5 MHz, Vdd = 2.5V to 3.3V

No load condition, f = 148.5 MHz, Vdd = 1.8V

f = 148.5 MHz, Vdd = 2.5V to 3.3V, OE = GND, Output in high-Z state

f = 148.5 MHz, Vdd = 1.8V, OE = GND, Output in high-Z state

= GND, Vdd = 2.5V to 3.3V, Output is weakly pulled down

= GND, Vdd = 1.8V, Output is weakly pulled down

Rev 1.01

August 13, 2020

www.sitime.com

SiT9045

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Table 1. Electrical Characteristics

(continued)

Parameters

Acceleration (g) sensitivity,

Gamma Vector

Symbol

F_g

Min.

–

Typ.

–

Max.

0.1

Unit

ppb/g

Condition

Low sensitivity grade; total gamma over 3 axes; 15 Hz to 2 kHz; MIL-

PRF-55310, computed per section 4.8.18.3.1

Rugged Characteristics

LVCMOS Output Characteristics

Duty Cycle

Rise/Fall Time

Output High Voltage

Tr, Tf

VOH

–

90%

–

1.2

–

2.0

–

Vdd

f = 1 to 137 MHz

f = 137.000001 to 150 MHz

20% - 80%, default derive strength

IOH = -4 mA (Vdd = 3.0V or 3.3V)

IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)

IOH = -2 mA (Vdd = 1.8V)

IOL = 4 mA (Vdd = 3.0V or 3.3V)

IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)

IOL = 2 mA (Vdd = 1.8V)

Output Low Voltage

VOL

–

10%

Vdd

Input Characteristics

Input High Voltage

Input Low Voltage

Input Leakage Current

VIH

VIL

70%

–

Startup Time

Enable/Disable Time

Resume Time

Spread Enable Time

Spread Disable Time

Cycle-to-cycle jitter

T_start

T_oe

T_resume

T_sde

T_sdde

T_ccj

–

Note:

Contact SiTime

for ±20 ppm options.

–

-2.3

2.8

-24.6

3.2

–

10.5

10.8

–

30%

–

215

–

Vdd

µA

µs

Jitter

f = 148.5 MHz, Vdd = 2.5 to 3.3V, Spread = ON (or OFF)

f = 148.5 MHz, Vdd = 1.8V, Spread = ON (or OFF)

Pin 1, OE or

Pin1,

logic low

Pin1,

logic high

Pin1, OE / SD logic low

Pin1, OE / SD logic high

Measured from the time Vdd reaches its rated minimum value

f = 148.5 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles

Measured from the time ST pin crosses 50% threshold

Measured from the time SD pin crosses 50% threshold

Startup and Resume Timing

Table 2. Spread Spectrum %

[3]

Ordering Code

Center Spread

(%)

±0.125

±0.250

±0.390

±0.515

±0.640

±0.765

±0.905

±1.030

±1.155

±1.280

±1.420

±1.545

±1.670

±1.795

±1.935

±2.060

Down Spread

(%)

-0.25

-0.50

-0.78

-1.04

-1.29

-1.55

-1.84

-2.10

-2.36

-2.62

-2.91

-3.18

-3.45

-3.71

-4.01

-4.28

Table 3. Spread Profile

[2,3]

Spread Profile

Triangular

Hershey-kiss

Random

Notes:

2. In both Triangular and Hershey-kiss profiles, modulation rate is

employed with a frequency of ~31.25 kHz. In random profile,

modulation rate is ~ 8.6 kHz.

3. The random profile supports up to ±1.030% center spread or -

2.10% down spread (ordering codes A through H).

Rev 1.01

Page 2 of 13

www.sitime.com

SiT9045

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Table 4. Pin Description

Symbol

OE /

NC / SD

Output

Enable

Standby

Functionality

[4]

: specified frequency output

L: output is high impedance. Only output driver is disabled.

H : specified frequency output

L: output is low (week pull down). Device goes to sleep mode.

Supply current reduced to I_std.

Pin1 has no function (Any voltage between 0 and Vdd or Open)

H: Spread = ON

L: Spread = OFF

Electrical ground

Oscillator output

Power supply voltage

[5]

[4]

Top View

OE /

NC / SD

VDD

No Connect

Spread

Disable

Notes:

GND

OUT

VDD

Power

Output

Power

GND

OUT

Figure 1. Pin Assignments

4. In OE or

mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.

5. A capacitor of value 0.1 µF or higher between Vdd and GND is required.

Table 5. Absolute Maximum Limits

Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of

the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.

Parameter

Storage Temperature

Vdd

Electrostatic Discharge

Soldering Temperature (follow standard Pb free soldering guidelines)

Junction Temperature

[6]

Note:

6. Exceeding this temperature for extended period of time may damage the device.

Min.

-65

-0.5

–

Max.

150

2000

260

150

Unit

°C

Table 6. Maximum Operating Junction Temperature

[7]

Max Operating Temperature (ambient)

85°C

105°C

125°C

Note:

7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.

Maximum Operating Junction Temperature

95°C

115°C

135°C

Table 7. Environmental Compliance

Parameter

Mechanical Shock

Mechanical Vibration

Temperature Cycle

Solderability

Moisture Sensitivity Level

Condition/Test Method

MIL-STD-883F, Method 2002

MIL-STD-883F, Method 2007

JESD22, Method A104

MIL-STD-883F, Method 2003

MSL1 @ 260°C

Rev 1.01

Page 3 of 13

www.sitime.com

SiT9045

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Timing Diagrams

Vdd

90% Vdd

Vdd

50% Vdd

T_resume

Pin 4 Voltage

T_start

No Glitch

[8]

during start up

ST Voltage

CLK Output

T_start: Time to start from power-off

CLK Output

T_resume: Time to resume from ST

Figure 2. Startup Timing

Figure 3. Standby Resume Timing (ST Mode Only)

Vdd

50% Vdd

OE Voltage

T_oe

Vdd

OE Voltage

50% Vdd

T_oe

CLK Output

T_oe: Time to re-enable the clock output

CLK Output

T_oe: Time to put the output in High Z mode

Figure 4. OE Enable Timing (OE Mode Only)

Figure 5. OE Disable Timing (OE Mode Only)

Vdd

50% Vdd

SD Voltage

T_sde

SD Voltage

Vdd

50% Vdd

Frequency

Deviation (%)

T_sdde

Modulation period = 32µs (31.25kHz)

Time (s)

Frequency

Deviation (%)

Time (s)

Figure 6. SD Enable Timing (SD Mode Only)

Note:

8. SiT9045 has “no runt” pulses and “no glitch” output during startup or resume.

Figure 7. SD Diable Timing (SD Mode Only)

Rev 1.01

Page 4 of 13

www.sitime.com

SiT9045

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Performance Plots

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

5.4

8.0

Current Consumption (mA)

5.2

5.0

4.8

4.6

4.4

100

120

140

OE Disable Current (mA)

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

100

120

140

Frequency (MHz)

Figure 8. Current Consumption vs Frequency

Figure 9. OE Disable Current vs Frequency

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

DUT1

DUT8

DUT15

DUT2

DUT9

DUT16

DUT3

FUT10

DUT17

DUT4

DUT11

DUT18

DUT5

DUT12

DUT19

DUT6

DUT13

DUT20

DUT7

DUT14

2.5

2.0

Frequency stability (ppm)

100

120

140

Standby Current (µA)

1.5

1.0

0.5

0.0

-5

-10

-15

-20

-40

-20

100

120

Frequency (MHz)

Temperature (°C)

Figure 10. Standby Current vs Frequency

Figure 11. Frequency vs Temperature

1.8V

2.5V

2.8V

3.0V

3.3V

Peak Cycle -to - Cycle Jitter (ps)

100

120

140

Frequency (MHz)

Figure 12. Cycle-to-cycle Jitter vs Frequency

(Spread profile: Triangular, Spread type: center,

Spread percentage: ±2.060%)

Rev 1.01

Page 5 of 13

www.sitime.com

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

Recommended Resources

Fireproof and anti-theft telephone intelligent alarm circuit-dial circuit

CR1 series soft starter circuit without bypass contactor

Parking and incoming call alarm circuit (3)

MN6014/S infrared remote control transmitter circuit

LED-parallel LED digital tube static display circuit (common anode)

Remote control infrared detection circuit

Cargo Transportation Status Tracking System: [Part 2] - Building the Hardware Environment and Development Environment: [size=4][color=#000000]Last time we said that the core board + STLCX01V1 expansion board is needed to realize the cargo transportation status tracking system. So the first thing to do is to prepare th...; chris_shang MEMS sensors

ADC0808 design a digital voltmeter problem, no numbers are displayed: [i=s]This post was last edited by Errenyiyi on 2017-12-2 00:37[/i] [i][i][i]. . . [/i][/i][/i]...; 二人了一 MCU

[Repost] Things to note when learning and designing FPGA: [Reprint address] [url] http://www.eechina.com/thread-128029-1-1.html [/ url] [color=#1f90de][font=Arial,] [url=http://www.eechina.com/keyword/FPGA] FPGA [/ url] [/font] [/color] [color=#000][font=Ari...; chenzhufly FPGA/CPLD

Nvidia launches Parker, a new generation of mobile processors, which will be perfectly adapted for self-driving cars: Nvidia, a giant in the manufacture of graphics processing chips, has such a keen sense of the market that it has extended its tentacles to the currently very popular self-driving cars, focusing on the...; hrconn2 Automotive Electronics

Some suggestions for Altera SoC activities: [align=left][color=#0000ff]Altera SoC activities have been carried out for more than 2 months. Everyone must have worked very hard during this period. SoC itself is a brand-new architecture, involving...; chenzhufly FPGA/CPLD

Application of CPLD in IGBT driver design: Abstract: This paper introduces a practical CPLD design of IGBT drive signal conversion circuit, and gives the simulation waveform of the design. Keywords: PWM CPLD IGBT VHDL Top-down With the continu...; eeleader Industrial Control Electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components