A1415A-PL84C datasheet, PDF - EEWORLD Datasheet

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A1415A-PL84C: DescriptionIC fpga 70 I/O 84plcc; CategoryProgrammable logic devices Programmable logic; File Size4MB，90 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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A1415A-PL84C Overview

IC fpga 70 I/O 84plcc

A1415A-PL84C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	QCCJ,
Reach Compliance Code	compliant
Other features	MAX 70 I/OS
maximum clock frequency	125 MHz
Combined latency of CLB-Max	3 ns
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Humidity sensitivity level	3
Configurable number of logic blocks	200
Equivalent number of gates	1500
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	200 CLBS, 1500 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	29.3116 mm
Base Number Matches	1

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Revision 3

Accelerator Series FPGAs – ACT 3 Family

Features

• Up to 10,000 Gate Array Equivalent Gates (up to 25,000

equivalent PLD Gates)

• Highly Predictable Performance with 100% Automatic Place-

and-Route

• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)

• Up to 186 MHz On-Chip Performance (–1 Speed Grade)

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

Table 1 • ACT 3 Family Product Information

Device

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Package (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

Logic Modules

S-Module

C-Module

Dedicated Flip-Flops

User I/Os (maximum)

Chip-to-Chip

(MHz)

Accumulators (16-bit, MHz)

Loadable Counter (16-bit, MHz)

Prescaled Loadable Counters (16-bit, MHz)

Datapath, Shift Registers (MHz)

Clock-to-Output (pad-to-pad, ns)

Packages

(by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

CQFP

PG100

PL84

PQ100

–

VQ100

–

PG133

PL84

PQ100, PQ160

–

VQ100

–

CQ132

PG175

PL84

PQ160

–

VQ100

TQ176

–

PG207

–

PQ160, PQ208

–

TQ176

BG225

CQ196

PG257

–

RQ208

–

BG313

CQ256

1,500

3,750

200

104

264

186

9.0

2,500

6,250

310

160

150

360

100

186

9.0

4,000

10,000

100

564

288

276

568

140

186

9.5

6,000

15,000

150

848

432

416

768

168

150

10.0

10,000

25,000

250

100

1,377

697

680

1,153

228

150

10.5

A1415

A1425

A1440

A1460

A14100

•

More than 500 Macro Functions

Replaces up to Twenty 32 Macro-Cell CPLDs

Replaces up to One Hundred 20-Pin PAL

Packages

Up to 1,153 Dedicated Flip-Flops

VQFP, TQFP, BGA, and PQFP Packages

Nonvolatile, User Programmable

Fully Tested Prior to Shipment

5.0 V and 3.3 V Versions

Optimized for Logic Synthesis Methodologies

Low Power CMOS Technology

Maximum Performance

(worst-case commercial, –1 speed grade)

Notes:

1. One flip-flop per S0Module, two flip-flops per I/O Module.

2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.

3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the

"System Performance Model" on page 1-1

and

Table 1-1 on page 1-2.

4. See the

"Product Plan" table on page III

for package availability.

5. Discontinued device and package combination.

6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product

Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:

PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004

January 2012

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