INTEGRATED CIRCUITS
DATA SHEET
PCD5003A
Enhanced Pager Decoder for
POCSAG
Product specification
File under Integrated Circuits, IC17
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
7.33
7.34
7.35
7.36
7.37
7.38
7.39
7.40
7.41
7.42
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Introduction
The POCSAG paging code
Error correction
Operating states
ON status
OFF status
Reset
Bit rates
Oscillator
Input data processing
Battery saving
Synchronization strategy
Call termination
Enhanced call termination
Call data output format
Sync word indication
Error type indication
Data transfer
Receiver and oscillator control
External receiver control and monitoring
Demodulator quick charge
Battery condition input
Synthesizer control
Serial microcontroller interface
Decoder I
2
C-bus access
External interrupt
Interrupt Masking
Status/control register
Pending interrupts
Out-of-range Indication
Real-time clock
Periodic interrupt
Received call delay
Alert generation
Alert cadence register (03H; write)
Acoustic alert
Vibrator alert
LED alert
Warbled alert
Direct alert control
Alert priority
Cancelling alerts
2
7.43
7.44
7.45
7.46
7.47
7.48
7.49
7.50
7.51
7.52
7.53
7.54
7.55
7.56
7.57
7.58
7.59
7.60
7.61
7.62
8
8.1
8.2
8.3
8.4
9
10
11
12
13
14
15
16
17
17.1
17.2
17.3
17.4
17.5
18
19
20
PCD5003A
Automatic POCSAG alerts
SRAM access
RAM write address pointer (06H; read)
RAM read address pointer (08H; read/write)
RAM data output register (09H; read)
EEPROM access
EEPROM address pointer (07H; read/write)
EEPROM data I/O register (0AH; read/write)
EEPROM access limitations
EEPROM read operation
EEPROM write operation
Invalid write address
Incomplete programming sequence
Unused EEPROM locations
Special programmed function allocation
Synthesizer programming data
Identifier storage allocation
Voltage doubler
Level-shifted interface
Signal test mode
OPERATING INSTRUCTIONS
Reset conditions
Power-on reset circuit
Reset timing
Initial programming
LIMITING VALUES
DC CHARACTERISTICS
DC CHARACTERISTICS (WITH VOLTAGE
CONVERTER)
OSCILLATOR CHARACTERISTICS
EEPROM CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
1
FEATURES
PCD5003A
•
Wide operating supply voltage range: 1.5 to 6.0 V
•
EEPROM programming requires only 2.0 V supply
•
Low operating current: 50
µA
typ. (ON),
25
µA
typ. (OFF)
•
Temperature range:
−25
to +70
°C
•
“CCIR Radio paging Code No. 1”
(POCSAG)
compatible
•
512, 1200 and 2400 bits/s data rates using 76.8 kHz
crystal
•
Built-in data filter (16-times oversampling) and bit clock
recovery
•
Advanced ACCESS
®
synchronization algorithm
•
2-bit random and (optional) 4-bit burst error correction
•
Up to 6 user addresses Receiver Identity Codes (RICs),
each with 4 functions/alert cadences
•
Up to 6 user address frames, independently
programmable
•
Optional automatic call termination when bit error rate is
high
•
Standard POCSAG sync word, plus up to 4 user
programmable sync words
•
Received data inversion (optional)
•
Call alert via beeper, vibrator or LED
•
2-level acoustic alert using single external transistor
•
Alert control: automatic (POCSAG type), via cadence
register or alert input pin
•
Separate power control of receiver and RF-oscillator for
battery economy
•
Dedicated pin for easy control of superheterodyne
receiver
•
Synthesizer set-up and control interface (3-line serial)
•
On-chip EEPROM for storage of user addresses (RICs),
pager configuration and synthesizer data
•
On-chip SRAM buffer for message data
4
ORDERING INFORMATION
TYPE
NUMBER
PCD5003AH
PACKAGE
NAME
LQFP32
DESCRIPTION
plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
VERSION
SOT358-1
•
Slave I
2
C-bus interface to microcontroller for transfer of
message data, status/control and EEPROM
programming (data transfer at up to 400 kbits/s)
•
Wake-up interrupt for microcontroller, programmable
polarity
•
Direct and I
2
C-bus control of operating status (ON/OFF)
•
Battery-low indication (external detector)
•
Out-of-range condition indication
•
Real-time clock reference output
•
On-chip voltage doubler
•
Interfaces directly to UAA2080 and UAA2082 paging
receivers.
2
APPLICATIONS
•
Display pagers, basic alert-only pagers
•
Information services
•
Personal organizers
•
Telepoint
•
Telemetry/data transmission.
3
GENERAL DESCRIPTION
The PCD5003A is a very low power POCSAG decoder
and pager controller. It supports data rates of 512,
1200 and 2400 bits/s using a single 76.8 kHz crystal.
On-chip EEPROM is programmable using a minimum
supply voltage of 2.0 V, allowing ‘over-the-air’
programming. The PCD5003A is fast I
2
C-bus compatible
(maximum 400 kbits/s).
1999 Jan 08
3
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
5
BLOCK DIAGRAM
PCD5003A
handbook, full pagewidth
EEPROM
ZSD
ZSC
ZLE
26
27
28
SYNTHESIZER
CONTROL
RESET
SET-UP
7
RST
EEPROM CONTROL
9
I
2
C-BUS
CONTROL
10
22
5
REGISTERS
AND
INTERRUPT
CONTROL
SDA
SCL
DQC
INT
RXE
ROE
24
25
RECEIVER
CONTROL
DECODING
DATA
CONTROL
POCSAG
SYNCHRONIZATION
RDI
23
DATA FILTER
AND
CLOCK
RECOVERY
MAIN DECODER
RAM
CONTROL
21
30
BAT
VIB
LED
ATL
ATH
ALC
REF
CCN
CCP
VPO
VPR
RAM
3
CLOCK
CONTROL
MASTER
DIVIDER
TIMER
REFERENCE
ALERT
GENERATION
AND
CONTROL
31
1
32
2
DON
TS1
TS2
XTAL1
XTAL2
16
20
18
17
OSCILLATOR
6, 19
n.c.
11
VDD
TEST
CONTROL
VOLTAGE
DOUBLER
AND LEVEL
SHIFTER
12, 29
4
15
14
13
8
PCD5003A
MGL568
VSS
Fig.1 Block diagram.
1999 Jan 08
4
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
6
PINNING
DESCRIPTION
alert LOW-level output
alert control input (normally LOW by
internal pull-down)
direct ON/OFF input (normally LOW by
internal pull-down)
real-time clock frequency reference
output
interrupt output
not connected
reset input (normally LOW by internal
pull-down)
external positive voltage reference
input
I
2
C-bus serial data input/output
I
2
C-bus serial clock input
main positive supply voltage
main negative supply voltage
voltage converter positive output
voltage converter shunt capacitor
(positive side)
voltage converter shunt capacitor
(negative side)
SYMBOL PIN
TS1
XTAL2
XTAL1
n.c.
TS2
BAT
DQC
RDI
RXE
ROE
ZSD
ZSC
ZLE
V
SS
VIB
LED
ATH
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PCD5003A
SYMBOL PIN
ATL
ALC
DON
REF
INT
n.c.
RST
V
PR
SDA
SCL
V
DD
V
SS
V
PO
CCP
CCN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DESCRIPTION
test input 1 (normally LOW by internal
pull-down)
decoder crystal oscillator output
decoder crystal oscillator input
not connected
test input 2 (normally LOW by internal
pull-down)
battery sense input
demodulator quick charge output
received POCSAG data input
receiver circuit enable output
receiver oscillator enable output
synthesizer serial data output
synthesizer serial clock output
synthesizer latch enable output
main negative supply voltage
vibrator motor drive output
LED drive output
alert HIGH-level output
28 ZLE
30 VIB
handbook, full pagewidth
25 ROE
32 ATH
27 ZSC
26 ZSD
31 LED
29 VSS
ATL
ALC
DON
1
2
3
24 RXE
23 RDI
22 DQC
21 BAT
REF 4
INT 5
n.c.
RST
VPR
6
7
8
PCD5003AH
20 TS2
19 n.c.
18 XTAL1
17 XTAL2
SCL 10
VDD 11
VSS 12
VPO 13
CCP 14
CCN 15
SDA 9
TS1 16
MGL569
Fig.2 Pin configuration.
1999 Jan 08
5
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