F271-BAG5-T-TR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> F271-BAG5-T-TR

F271-BAG5-T-TR: Descriptionmcu 16bit 128k flash 144-tqfp; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，180 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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F271-BAG5-T-TR Overview

mcu 16bit 128k flash 144-tqfp

F271-BAG5-T-TR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, TQFP-144
Contacts	144
Reach Compliance Code	compliant
Is Samacsys	N
Has ADC	YES
Address bus width	23
bit size	16
CPU series	ST10
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width	16
JESD-30 code	S-PQFP-G144
JESD-609 code	e3
length	20 mm
Humidity sensitivity level	3
Number of I/O lines	111
Number of terminals	144
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	8192
rom(word)	131072
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	48 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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ST10F271B

ST10F271E

16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM

Features

■

16-bit CPU with DSP functions

– 31.25ns instruction cycle time at 64MHz

max CPU clock

– Multiply/accumulate unit (MAC) 16 x 16-bit

multiplication, 40-bit accumulator

– Enhanced boolean bit manipulations

– Single-cycle context switching support

On-chip memories

– 256 Kbyte Flash memory (32-bit fetch)

– Single voltage Flash memories with

erase/program controller and 100K

erasing/programming cycles.

– Up to 16 Mbyte linear address space for

code and data (5 Mbytes with CAN or I

– 2 Kbyte internal RAM (IRAM)

– 10/18 Kbyte extension RAM (XRAM)

– Programmable external bus configuration &

characteristics for different address ranges

– Five programmable chip-select signals

– Hold-acknowledge bus arbitration support

Interrupt

– 8-channel peripheral event controller for

single cycle interrupt driven data transfer

– 16-priority-level interrupt system with 56

sources, sampling rate down to 15.6ns

■

PQFP144 (28 x 28 x 3.4mm)

(Plastic Quad Flat Package)

■

A/D converter

– 24-channel 10-bit

– 3

µs

minimum conversion time

■

-O

■

Serial channels

– Two synch. / asynch. serial channels

– Two high-speed synchronous channels

– One I

C standard interface

TQFP144 (20 x 20 x 1.4mm)

(Thin Quad Flat Package)

2 CAN 2.0B interfaces operating on 1 or 2 CAN

busses (64 or 2x32 message, C-CAN version)

Fail-safe protection

– Programmable watchdog timer

– Oscillator watchdog

On-chip bootstrap loader

Clock generation

– On-chip PLL with 4 to 8 MHz oscillator

– Direct or prescaled clock input

Real time clock and 32 kHz on-chip oscillator

Up to 111 general purpose I/O lines

– Individually programmable as input, output

or special function

– Programmable threshold (hysteresis)

Idle, power down and stand-by modes

Single voltage supply: 5V ±10%

Timers

– Two multi-functional general purpose timer

units with 5 timers

Two 16-channel capture / compare units

4-channel PWM unit + 4-channel XPWM

■

July 2006

Rev 1

1/180

www.st.com

Contents

ST10F271B/ST10F271E

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1

5.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.1

5.2.2

5.2.3

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3

5.4

Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4.1

5.4.2

5.4.4

5.4.6

5.4.8

5.4.3

5.4.5

5.4.7

5.4.9

Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

-O

5.4.10

5.4.11

Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.5

Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Flash non volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 37

Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 38

. . . . . . . . . . . . . . . Flash non volatile access protection register 1 high 39

Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 38

2/180

ST10F271B/ST10F271E

5.5.6

5.5.7

5.5.8

5.5.9

Contents

XBus flash volatile temporary access unprotection register (XFVTAUR0) .

Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.6

5.7

Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.1

6.2

6.3

Selection among user-code, standard or selective bootstrap . . . . . . . . . . 45

Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 46

6.3.1

6.3.2

6.3.3

Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.1

7.2

7.3

Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

-O

9.1

9.2

MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 51

External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.1

11.2

GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3/180

Contents

ST10F271B/ST10F271E

13.2

I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.2.1

13.2.2

Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Input threshold control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

13.3

Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

15.1

15.2

15.3

15.4

Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 70

ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 72

I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17.1

17.2

Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

-O

20.1

20.2

20.3

20.4

20.5

20.6

20.7

20.8

20.9

Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.1

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4/180

ST10F271B/ST10F271E

Contents

21.2

Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.2.1

21.2.2

Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

21.3

Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

21.3.1

21.3.2

21.3.3

21.3.4

Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 111

23.1

23.2

23.3

23.4

Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

24.1

24.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

-O

24.3

24.4

24.5

24.6

24.7

24.7.1

24.7.2

24.7.4

24.7.3

Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

24.8

AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

24.8.1

24.8.2

24.8.3

24.8.4

24.8.5

24.8.6

Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5/180

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