Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5604P
Rev. 8, 07/2012
MPC5604P
144 LQFP
20 mm x 20 mm
100 LQFP
14 mm x 14 mm
Qorivva MPC5604P
Microcontroller Data Sheet
•
Up to 64 MHz, single issue, 32-bit CPU core complex
(e200z0h)
— Compliant with Power Architecture embedded
category
— Variable Length Encoding (VLE)
Memory organization
— Up to 512 KB on-chip code flash memory with ECC
and erase/program controller
— Optional 64 (4 × 16) KB on-chip data flash memory
with ECC for EEPROM emulation
— Up to 40 KB on-chip SRAM with ECC
Fail safe protection
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
Nexus L2+ interface
Interrupts
— 16-channel eDMA controller
— 16 priority level controller
General purpose I/Os individually programmable as input,
output or special function
2 general purpose eTimer units
— 6 timers each with up/down count capabilities
— 16-bit resolution, cascadable counters
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
Communications interfaces
— 2 LINFlex channels (LIN 2.1)
— 4 DSPI channels with automatic chip select
generation
— 1 FlexCAN interface (2.0B Active) with 32 message
objects
1 safety port based on FlexCAN with 32 message
objects and up to 7.5 Mbit/s capability; usable as
second CAN when not used as safety port
— 1 FlexRay™ module (V2.1) with selectable dual or
single channel support, 32 message objects and up to
10 Mbit/s
Two 10-bit analog-to-digital converters (ADC)
— 2 × 15 input channels, 4 channels shared between the
two ADCs
— Conversion time < 1 µs including sampling time at
full precision
— Programmable Cross Triggering Unit (CTU)
— 4 analog watchdogs with interrupt capability
On-chip CAN/UART bootstrap loader with Boot Assist
Module (BAM)
1 FlexPWM unit
— 8 complementary or independent outputs with ADC
synchronization signals
— Polarity control, reload unit
— Integrated configurable dead time unit and inverter
fault input pins
— 16-bit resolution, up to 2 × f
CPU
— Lockable configuration
Clock generation
— 4–40 MHz main oscillator
— 16 MHz internal RC oscillator
— Software controlled FMPLL capable of speeds as fast
as 64 MHz
Voltage supply
— 3.3 V or 5 V supply for I/Os and ADC
— On-chip single supply voltage regulator with external
ballast transistor
—
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Operating temperature ranges: –40 to 125 °C or –40
to 105 °C
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale, Inc., 2008–2012. All rights reserved.
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High performance e200z0 core processor. . . . . .7
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Enhanced direct memory access (eDMA) . . . . . .8
1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5.5 Static random access memory (SRAM). . . . . . . .9
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . .9
1.5.7 System status and configuration module
(SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5.8 System clocks and clock generation . . . . . . . . .10
1.5.9 Frequency-modulated phase-locked loop
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . 11
1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . 11
1.5.13 System timer module (STM) . . . . . . . . . . . . . . . 11
1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . . 11
1.5.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . .12
1.5.16 System integration unit – Lite (SIUL) . . . . . . . . .12
1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . .12
1.5.18 Error correction status module (ECSM). . . . . . .13
1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .13
1.5.20 Controller area network (FlexCAN) . . . . . . . . . .13
1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . .14
1.5.22 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.5.23 Serial communication interface module
(LINFlex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.24 Deserial serial peripheral interface (DSPI) . . . .15
1.5.25 Pulse width modulator (FlexPWM) . . . . . . . . . .16
1.5.26 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.27 Analog-to-digital converter (ADC) module . . . . .17
1.5.28 Cross triggering unit (CTU) . . . . . . . . . . . . . . . .18
1.5.29 Nexus development interface (NDI). . . . . . . . . .18
1.5.30 Cyclic redundancy check (CRC) . . . . . . . . . . . .19
1.5.31 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . .19
1.5.32 On-chip voltage regulator (VREG). . . . . . . . . . .19
Package pinouts and signal descriptions . . . . . . . . . . . . . . . .20
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 Power supply and reference voltage pins . . . . .21
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . .
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .
3.4 Recommended operating conditions . . . . . . . . . . . . . .
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Package thermal characteristics . . . . . . . . . . .
3.5.2 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . .
3.6 Electromagnetic interference (EMI) characteristics . . .
3.7 Electrostatic discharge (ESD) characteristics . . . . . . .
3.8 Power management electrical characteristics . . . . . . .
3.8.1 Voltage regulator electrical characteristics . . . .
3.8.2 Voltage monitor electrical characteristics . . . . .
3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . .
3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . .
3.10.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 DC electrical characteristics (5 V) . . . . . . . . . .
3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . .
3.10.4 Input DC electrical characteristics definition . .
3.10.5 I/O pad current specification. . . . . . . . . . . . . . .
3.11 Main oscillator electrical characteristics . . . . . . . . . . .
3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . .
3.13 16 MHz RC oscillator electrical characteristics . . . . . .
3.14 Analog-to-digital converter (ADC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 Input impedance and ADC accuracy . . . . . . . .
3.14.2 ADC conversion characteristics . . . . . . . . . . . .
3.15 Flash memory electrical characteristics. . . . . . . . . . . .
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . .
3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . .
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . .
3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . .
3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . .
4.1.1 144 LQFP mechanical outline drawing . . . . . .
4.1.2 100 LQFP mechanical outline drawing . . . . . .
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix AAbbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MPC5604P Microcontroller Data Sheet, Rev. 8
2
Freescale
1
1.1
Introduction
Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5603P/4P series of
microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical
characteristics. For functional characteristics, refer to the device reference manual.
1.2
Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive
application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis
applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag
applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology.
The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture
embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with users implementations.
1.3
Device comparison
Table 1. MPC5604P device comparison
Feature
Code flash memory (with ECC)
Data flash memory / EE option (with ECC)
SRAM (with ECC)
Processor core
Instruction set
CPU performance
FMPLL (frequency-modulated phase-locked loop)
module
INTC (interrupt controller) channels
PIT (periodic interrupt timer)
eDMA (enhanced direct memory access) channels
FlexRay
1
FlexCAN (controller area network)
Safety port
FCU (fault collection unit)
CTU (cross triggering unit)
36 KB
32-bit e200z0h
VLE (variable length encoding)
0–64 MHz
2
147
1 (includes four 32-bit timers)
16
Optional feature
2
2,3
Yes (via second FlexCAN module)
Yes
Yes
MPC5603P
384 KB
64 KB (optional feature)
40 KB
MPC5604P
512 KB
Table 1
provides a summary of different members of the MPC5604P family and their features to enable a comparison among
the family members and an understanding of the range of functionality offered within this family.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
3
Table 1. MPC5604P device comparison (continued)
Feature
eTimer
FlexPWM (pulse-width modulation) channels
ADC (analog-to-digital converter)
LINFlex
DSPI (deserial serial peripheral interface)
CRC (cyclic redundancy check) unit
JTAG controller
Nexus port controller (NPC)
Supply
Digital power supply
Analog power supply
Internal RC oscillator
External crystal oscillator
Packages
Temperature
1
2
3
4
MPC5603P
MPC5604P
2 (16-bit, 6 channels)
8 (capturing on X-channels)
2 (10-bit, 15-channel
4
)
2
4
Yes
Yes
Yes (Level 2+)
3.3 V or 5 V single supply with external transistor
3.3 V or 5 V
16 MHz
4–40 MHz
100 LQFP
144 LQFP
Standard ambient temperature
–40 to 125 °C
32 message buffers, selectable single or dual channel support
Each FlexCAN module has 32 message buffers.
One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
Four channels shared between the two ADCs
1.4
Block diagram
Figure 1
shows a top-level block diagram of the MPC5604P MCU.
MPC5604P Microcontroller Data Sheet, Rev. 8
4
Freescale
External ballast
1.2 V regulator
control
XOSC
16 MHz
RC oscillator
FMPLL_0
(System)
FMPLL_1
(FlexRay, MotCtrl)
JTAG
Nexus port
controller
eDMA
16 channels
Master
e200z0 Core
32-bit
general
purpose
registers
Integer
execution
unit
Special
purpose
registers
Instruction
unit
Exception
handler
Variable
length
encoded
instructions
Load/store
unit
Interrupt
controller
Branch
prediction
unit
Nexus 2+
Instruction
32-bit
Master
Data
32-bit
Master
FlexRay
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
Slave
Slave
Slave
MC_RGM
MC_CGM
MC_ME
WKPU
ECSM
FCU
SWT
Code Flash
(with ECC)
Data Flash
(with ECC)
SRAM
(with ECC)
Peripheral bridge
1.2 V Rail V
REG
2×
eTimer (6 ch)
Channels
0–10
Legend:
ADC
BAM
CRC
CTU
DSPI
ECSM
eDMA
eTimer
FCU
Flash
FlexCAN
FlexPWM
FMPLL
INTC
JTAG
Analog-to-digital converter
Boot assist module
Cyclic redundancy check
Cross triggering unit
Deserial serial peripheral interface
Error correction status module
Enhanced direct memory access
Enhanced timer
Fault collection unit
Flash memory
Controller area network
Flexible pulse width modulation
Frequency-modulated phase-locked loop
Interrupt controller
JTAG controller
LINFlex
MC_CGM
MC_ME
MC_PCU
MC_RGM
PIT
SIUL
SRAM
SSCM
STM
SWT
WKPU
XOSC
XBAR
Serial communication interface (LIN support)
Clock generation module
Mode entry module
Power control unit
Reset generation module
Periodic interrupt timer
System integration unit Lite
Static random-access memory
System status and configuration module
System timer module
Software watchdog timer
Wakeup unit
External oscillator
Crossbar switch
Figure 1. MPC5604P block diagram
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
5
Channels
0–10
Shared
channels
11–14
Safety port
FlexPWM
FlexCAN
2×
LINFlex
10-bit
ADC_0
10-bit
ADC_1
SSCM
4×
DSPI
CTU
BAM
CRC
STM
SIUL
PIT
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