INTEGRATED CIRCUITS
DATA SHEET
PCA16xx series
32 kHz watch circuits with
EEPROM
Product specification
Supersedes data of 1997 Apr 21
File under Integrated Circuits, IC16
1997 Dec 12
Philips Semiconductors
Product specification
32 kHz watch circuits with EEPROM
FEATURES
•
32 kHz oscillator, amplitude regulated with excellent
frequency stability
•
High immunity of the oscillator to leakage currents
•
Time calibration electrically programmable and
reprogrammable (via EEPROM)
•
A quartz crystal is the only external component required
•
Very low current consumption; typically 170 nA
•
Detector for silver-oxide or lithium battery voltage levels
•
Indication for battery end-of-life
ORDERING INFORMATION
TYPE
NUMBER
PCA1601U/10
PCA1602T
PCA1603U/7
PCA1604U
PCA1604U/10
PCA1605U/7
PCA1606U/10
PCA1607U
PCA1608U
PCA1611U
PCA1621U/7
PCA1621U/10
PCA1622U
PCA1623U/7
PCA1624U
PCA1625U/7
PCA1626U
PCA1627U/7
PCA1628U
PCA1629U/7
Note
PACKAGE
(1)
NAME
−
PMFP8
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
chip on foil
plastic micro flat package; 8 leads (straight)
chip with bumps on tape
chip in tray
chip on foil
chip with bumps on tape
chip on foil
chip in tray
chip in tray
chip in tray
chip with bumps on tape
chip on foil
chip in tray
chip with bumps on tape
chip in tray
chip with bumps on tape
chip in tray
chip with bumps on tape
chip in tray
chip with bumps on tape
DESCRIPTION
PCA16xx series
•
Stop function for accurate timing
•
Power-on reset for fast testing
•
Various test modes for testing the mechanical parts of
the watch and the IC.
GENERAL DESCRIPTION
The PCA16xx series devices are CMOS integrated circuits
specially suited for battery-operated,
quartz-crystal-controlled wrist-watches, with bipolar
stepping motors.
VERSION
−
SOT144-1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1. Figure 1 and Chapter “Package outline” show details of standard package, available for specified devices and for
large orders only.
Chapter “Chip dimensions and bonding pad locations” shows exact pad locations for other delivery formats.
1997 Dec 12
2
Philips Semiconductors
Product specification
32 kHz watch circuits with EEPROM
PINNING
SYMBOL
V
SS
TEST
OSC IN
OSC OUT
V
DD
M1
M2
RESET
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
ground (0 V)
test output
oscillator input
oscillator output
positive supply voltage
motor 1 output
motor 2 output
reset input
Customer testing
OSC IN
OSC OUT
3
4
VSS
TEST
1
2
PCA16xx series
8
7
RESET
M2
M1
V DD
PCA16xxT
6
5
MSA973
Fig.1 Pin configuration, PCA16xxT, (PMFP8).
FUNCTIONAL DESCRIPTION AND TESTING
Motor pulse
The motor pulse width (t
P
) and the cycle times (t
T
) are
given in Chapter “Available types”.
Voltage level detector
The supply voltage is compared with the internal voltage
reference V
LIT
and V
EOL
every minute. The first voltage
level detection is carried out 30 ms after a RESET.
Lithium mode
If a lithium voltage is detected (V
DD
≥
V
LIT
), the circuit will
operate in the lithium mode. The motor pulse will be
produced with a 75% duty factor.
Silver-oxide mode
If the voltage level detected is between V
LIT
and V
EOL
, the
circuit will operate in silver-oxide mode.
Battery end-of-life
(1)
If the battery end-of-life is detected (V
DD
≤
V
EOL
), the
motor pulse will be produced without chopping. To indicate
this condition, bursts of 4 pulses are produced every 4 s.
Power-on reset
For correct operation of the Power-on reset the rise time of
V
DD
from 0 V to 2.1 V should be less than 0.1 ms.
All resettable flip-flops are reset. Additionally the polarity of
the first motor pulse is positive: V
M1
−
V
M2
≥
0 V.
An output frequency of 32 Hz is provided at RESET (pin 8)
to be used for exact frequency measurement. Every
minute a jitter occurs as a result of time calibration, which
occurs 90 to 150 ms after disconnecting the RESET from
V
DD
.
Connecting the RESET to V
DD
stops the motor pulses
leaving them in a HIGH impedance 3-state condition and a
32 Hz signal without jitter is produced at the TEST pin.
A debounce circuit protects accidental stoppages due to
mechanical shock to the watch (t
DEB
= 14.7 to 123.2 ms).
Connecting RESET to V
SS
activates Tests 1 and 2 and
disables the time calibration.
Test 1, V
DD
> V
EOL
. Normal function takes place except
the voltage detection cycle (t
V
) is 125 ms and the cycle
time t
T1
is 31.25 ms. At pin TEST a minute signal is
available at 8192 times its normal frequency.
Test 2
(2)
, V
DD
< V
EOL
. The voltage detection cycle (t
V
) is
31.25 ms and the motor pulse period (t
T2
) = 31.25 ms.
Test and reset mode are terminated by disconnecting the
RESET pin.
Test 3, V
DD
> 5.1 V.
Motor pulses with a time period of
t
T3
= 31.25 ms and n
×
122
µs
are produced to check the
contents of the EEPROM. At pin TEST the motor pulse
period signal (t
T
) is available at 1024 times its normal
frequency. The circuit returns to normal operation when
V
DD
< 2.5 V between two motor pulses.
(2) Only applicable for types with the battery end-of-life detector.
(1) Only available for types with a 1 s motor pulse.
1997 Dec 12
3
Philips Semiconductors
Product specification
32 kHz watch circuits with EEPROM
Time calibration
Taking a normal quartz crystal with frequency 32768kHz,
frequency deviation (∆f/f) of
±15 ×
10
−6
and C
L
= 8.2 pF;
the oscillator frequency is offset (by using non-symmetrical
internal oscillator input and output capacitances of 10 pF
and 15 pF) such that the frequency deviation is
positive-only. This positive deviation can then be
compensated for to maintain time-keeping accuracy.
Once the positive frequency deviation is measured, a
corresponding number ‘n’ (see Table 1) is programmed
into the device’s EEPROM. This causes n pulses of
frequency 8192 Hz to be inhibited every minute of
operation, which achieves the required calibration.
The programming circuit is shown in Fig.2. The required
number n is programmed into EEPROM by varying V
DD
according to the steps shown in Fig.3, which are
explained below:
1. The positive quartz frequency deviation (∆f/f) is
measured, and the corresponding values of n are
found according to Table 1.
2. V
DD
is increased to 5.1 V allowing the contents of the
EEPROM to be checked from the motor pulse period
t
T3
at nominal frequency.
Table 1
Quartz crystal frequency deviation, n and t
T3
NUMBER OF
PULSES
(n)
0
1
2
.
.
.
63
PCA16xx series
3. V
DD
is decreased to 2.5 V during a motor pulse to
initialize a storing sequence.
4. The first V
DD
pulse to 5.1 V erases the contents of
EEPROM.
5. When the EEPROM is erased a logic 1 is at the TEST
pin.
6. V
DD
is increased to 5.1 V to read the data by pulsing
V
DD
n times to 4.5 V. After the n edge, V
DD
is
decreased to 2.5 V.
7. V
DD
is increased to 5.1 V to store n bits in the
EEPROM.
8. V
DD
is decreased to 2.5 V to terminate the storing
sequence and to return to operating mode.
9. V
DD
is increased to 5.1 V to check writing from the
motor pulse period t
T3
.
10. V
DD
is decreased to the operation voltage
between
two motor pulses to return to operating mode.
(Decreasing V
DD
during the motor pulse would restart
the programming mode).
The time calibration can be reprogrammed up to 100
times.
FREQUENCY
DEVIATION
∆f/f
(× 10
−6
)
0
(1)
+2.03
+4.06
.
.
.
+127.89
Notes
SIGNAL GENERATOR
t
T3
(ms)
V SS
31.250
(2)
31.372
31.494
.
.
.
38.936
32 kHz
OSC OUT
OSC IN
TEST
1
8
RESET
2
7
M2
M
PCA16xx
SERIES
3
6
M1
4
5
VDD
MSA975
1. Increments of 2.03
×
10
−6
/step.
2. Increments of 122
µs/step.
Fig.2 Circuit for programming the time calibration.
1997 Dec 12
4
1997 Dec 12
ERASURE
DATA INPUT
STORING
CHECKING
∆
V DDP
1
2
3
n
t T3
Philips Semiconductors
CONTENT CHECKING
I DD
5.1
4.5
t edge = 1
µs
0.1 ms
min.
3
4
5
6
7
8
9
10
32 kHz watch circuits with EEPROM
9
10
VDD (V)
5
t E = 5 ms
t S = 5 ms
(1)
(1)
(1)
2.5
1
2
1.5
0 (VSS)
MSA948
(1)
(1) Rise and fall time should be greater than 400
µs/V
for immediately correct checking.
PCA16xx series
Product specification
Fig.3 V
DD
for programming.
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