Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33888
Rev 3.0, 10/2004
Product Preview
Quad High-Side and Octal Low-Side
Switch for Automotive
The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mΩ and two 40 mΩ) and an integrated
IC control die consisting of eight low-side drivers (600 mΩ each) with
appropriate control, protection, and diagnostic features.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.
The 33888 is available
in
two power packages.
Features
• Dual 10 mΩ High Side, Dual 40 mΩ High Side, Octal 600 mΩ Low Side
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High Side Current Sense,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout
• SPI Reporting of Program Status and Fault
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity V
PWR
Protection
33888
33888A
SOLID STATE RELAY FOR
AUTOMOTIVE APPLICATIONS
Freescale Semiconductor, Inc...
Bottom View
PNB SUFFIX
APNB SUFFIX
CASE 1438-06
36-TERMINAL PQFN
(12 x 12)
Top View
FB SUFFIX
CASE 1315-03
64-TERMINAL PQFP
ORDERING INFORMATION
Device
PC33888PNB/R2
PC33888APNB/R2
MC33888FB/R2
-40°C to 125°C
Temperature
Range (T
A
)
Package
36 PQFN
64 PQFP
33888 Simplified Application Diagram
V
PWR
+5.0 V
+5.0 V
8 x Relay or LED
33888
4
MCU
A/D
A/D
V
PWR
FS V
DD
IHS0:IHS3
LS4:LS11
ILS
RST
SPI
HS3
WDIN
HS2
CSNS2-3
HS1
CSNS0-1
HS0
FSI
GND
Loads
4
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
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Freescale Semiconductor, Inc.
Table 1. Features Comparison: 33888 and 33888A
Parameter
Undervoltage Low-Side Output Shutdown
Low-Side Drain-to-Source ON Resistance
Symbol
V
PWRUV
R
DS(ON)
Condition
–
V
PWR
= 4.5 V;
V
DD
= 3.5 V
Extended Mode,
V
DD
= 3.4 V
33888
5.0 V
Not specified
33888A
3.0 V
8.0
Ω
For details,
see page
11
14
Recommended Frequency of SPI Operation
f
SPI
Not specified
2.1 MHz
(max)
17
V
DD
V
PWR
Freescale Semiconductor, Inc...
V
IC
I
UP
CS
SCLK
I
DWN
SO
SI
RST
WAKE
FS
IN0
IN1
IN2
IN3
ILS
SPI
3.0 MHz
Internal
Regulator
Over/Undervoltage
Protection
10 mΩ
Gate Driver
Selectable Current Limit
Open Load
HS0
Detection
Logic
Overtemperature
Detection
HS0
CSNS0-1
HS1
Gate Control and Fault 10 mΩ
HS1
Selectable Output Current
Recopy (Analog MUX)
Gate Control and Fault 40 mΩ
R
DWN
I
DWN
HS2
Selectable Output Current
Recopy (Analog MUX)
HS2
CSNS2-3
Gate Control and Fault 40 mΩ
HS3
V
IC
HS3
WDIN
Watchdog
Gate
Control
Clamp
Over-
temperature
I
LIM
Open Load
x8
FSI
LS4
LS5
LS6
LS7
LS8
LS9
LS10
LS11
GND
Figure 1. 33888 Simplified Internal Block Diagram
33888
2
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Transparent Top View of Package
V
PWR
2
LS11
LS10
GND
GND
V
DD
LS9
LS8
LS7
LS6
LS5
LS4
SO
FS
1
36
35
WDIN
FSI
RST
WAKE
GND
IHS1
IHS0
CSNS0-1
34
33
32
31
30
29
28
HS2
14
CS
SCLK
SI
ILS
GND
IHS3
16
17
18
19
20
21
22
23
13
12
11
10
9
8
7
6
5
4
3
15
GND
(Control Die)
Freescale Semiconductor, Inc...
IHS2
CSNS2-3
Internally Connected to V
PWR
24
V
PWR
(Power Die)
25
HS3
26
HS1
27
HS0
TERMINAL DEFINITIONS FOR PQFN
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
1
Terminal
Name
FS
Formal Name
Fault Status
(Active Low)
Positive Power Supply
Low-Side Output 4
Low-Side Output 6
Low-Side Output 8
Low-Side Output 10
Ground
Low-Side Output 5
Low-Side Output 7
Low-Side Output 9
Low-Side Output 11
Digital Drain Voltage (Power)
Definition
This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.
These terminal connects to the positive power supply and are the source input of
operational power for the device.
Each low-side terminal is one 0.6
Ω
low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.
These terminals serve as the ground for the source of the low-side output
transistors as well as the logic portion of the device.
Each low-side terminal is one 0.6
Ω
low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.
This is an external input terminal used to supply power to the SPI circuit.
2, 24
3
6
8
10
4, 11, 15,
20, 32
5
7
9
12
13
V
PWR
LS4
LS6
LS8
LS10
GND
LS5
LS7
LS9
LS11
V
DD
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Go to: www.freescale.com
33888
3
Freescale Semiconductor, Inc.
TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
14
Terminal
Name
SO
Formal Name
Serial Output
Definition
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low
CS
terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the
CS
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, f
SPI
, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
Each high-side input terminal is used to directly control only one designated high-
side output. These inputs may or may not be activated depending on the configured
state of the internal logic.
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
16
CS
Chip Select
(Active Low)
Freescale Semiconductor, Inc...
17
SCLK
Serial Clock
18
SI
Serial Input
19
ILS
Low-Side Input
21
22
30
31
23
29
IHS3
IHS2
IHS0
IHS1
CSNS2-3
CSNS0-1
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Current Sense 2-3
Current Sense 0-1
25
28
HS3
HS2
High-Side Output 3
High-Side Output 2
26
27
HS1
HS0
High-Side Output 1
High-Side Output 0
33
WAKE
Wake
33888
4
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
34
Terminal
Name
RST
Formal Name
Reset (Active Low)
Definition
This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until V
DD
is in regulation. This input has an
internal passive pulldown.
The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
35
FSI
Fail-Safe Input
Freescale Semiconductor, Inc...
36
WDIN
Watchdog Input
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33888
5
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