70T3599S200BC8 datasheet, PDF - EEWORLD Datasheet

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70T3599S200BC8: DescriptionIC sram 4.5mbit 200mhz 256cabga; Categorystorage; File Size402KB，28 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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70T3599S200BC8 Overview

IC sram 4.5mbit 200mhz 256cabga

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Features:

◆

HIGH-SPEED 2.5V

256/128/64K x 36

IDT70T3519/99/89S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Interrupt and Collision Detection Flags

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 208-pin

Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball

Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG is not supported on the 208-

pin PQFP package

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B B

WWW

2 3 3

L L R

B B

1 0

R R

1/0

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c 1b 0b 1a 0a

0a 1a 0b 1b 0c 1c 0d 1d

0/1

FT/PIPE

0/1

abc d

d cba

256/128/64K x 36

MEMORY

ARRAY

I/O

- I/O

35L

Din_L

Din_R

I/O

- I/O

35R

CLK

17L(1)

REPEAT

ADS

CNTEN

17R(1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

R /

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1 R

JTAG

TDO

COL

INT

COL

INT

(2)

NOTES:

1. Address A

is a NC for the IDT70T3599. Also, Addresses A

and A

are NC's for the IDT70T3589.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

(2)

5666 drw 01

MARCH 2014

DSC 5666/11

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