PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87354I
÷4/÷5 D
IFFERENTIAL
-
TO
-2.5V/3.3V
LVPECL C
LOCK
G
ENERATOR
F
EATURES
• 1 differential 2.5V/3.3V LVPECL / ECL output
• 1 CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 250MHz
• Input frequency: >1GHz
• Translates any single ended input signal to
3.3V LVPECL levels with resistor bias on nCLK input
• Output skew: 38ps (maximum)
• Part-to-part skew: 375ps (maximum)
• Propagation delay: 2.1ns (maximum)
• LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
• ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS87354I is a high performance ÷4/÷5 Dif-
ferential-to-2.5V/3.3V ECL/LVPECL Clock Genera-
HiPerClockS™
tor and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS. The
CLK, nCLK pair can accept most standard differ-
ential input levels. The ICS87354I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed output
and part-to-part skew characteristics make the ICS87354I ideal
for those clock distribution applications demanding well defined
performance and repeatability.
,&6
B
LOCK
D
IAGRAM
CLK
nCLK
R
÷
4
÷
5
0
1
Q
nQ
P
IN
A
SSIGNMENT
CLK
nCLK
MR
F_SEL
1
2
3
4
8
7
6
5
Vcc
Q
nQ
V
EE
MR
ICS87354I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
F_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87354AMI
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 27, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87354I
÷4/÷5 D
IFFERENTIAL
-
TO
-2.5V/3.3V
LVPECL C
LOCK
G
ENERATOR
Type
Input
Input
Input
Input
Power
Output
Power
Pullup
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6, 7
8
Name
CLK
nCLK
MR
F_SEL
V
EE
Q, nQ
V
CC
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Master reset. When LOW, outputs are enabled. When HIGH,
Pulldown divider is reset forcing Q output LOW and nQ output HIGH.
LVCMOS / LVTTL interface levels.
Selects divider value for Q, nQ outputs as described in table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3. F
UNCTION
T
ABLE
MR
1
0
0
F_SEL
X
0
1
Divide Value
Reset: Q output low, nQ output high
÷4
÷5
CLK
MR
Q
F
IGURE
1. T
IMING
D
IAGRAM
87354AMI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 27, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87354I
÷4/÷5 D
IFFERENTIAL
-
TO
-2.5V/3.3V
LVPECL C
LOCK
G
ENERATOR
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
TBD
Maximum
3.8
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
MR, F_SEL
MR, F_SEL
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-5
-150
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
87354AMI
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 27, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87354I
÷4/÷5 D
IFFERENTIAL
-
TO
-2.5V/3.3V
LVPECL C
LOCK
G
ENERATOR
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.65
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
0.9
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0, T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Input Frequency
Propagation Delay;
CLK to Q (Dif)
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3 , 4
Test Conditions
Minimum
Typical
>1
1.65
2.1
38
375
600
Maximum
Units
GHz
ns
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
Output Rise/Fall Time
20% to 80%
200
t
R
/ t
F
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87354AMI
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 27, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87354I
÷4/÷5 D
IFFERENTIAL
-
TO
-2.5V/3.3V
LVPECL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
CC
= 2V
Qx
SCOPE
V
CC
LVPECL
nQx
nCLK
V
CLK
PP
Cross Points
V
CMR
V
EE
= -1.8V ± -0.375V
V
EE
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
PART 1
nQx
Qx
PART 2
nQy
Qy
tsk(pp)
nQx
Qx
nQy
Qy
tsk(o)
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
nCLK
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
CLK
nQ
Q
t
PD
O
UTPUT
R
ISE
/F
ALL
T
IME
87354AMI
P
ROPAGATION
D
ELAY
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5
REV. A JUNE 27, 2003
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