PRELIMINARY
16:1 LVCMOS/LVTTL-TO-LVPECL/LVDS
CLOCK MULTIPLEXER
ICS859S1601I
Features
•
•
•
•
•
•
•
•
•
High speed 16:1 differential multiplexer
One differential LVPECL or LVDS output pair
Sixteen selectable LVCMOS/LVTTL clock inputs
CLKx can accept the following input levels: LVCMOS and
LVTTL
Maximum output frequency: 250MHz
Propagation delay: 1.0ns (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS859S1061I is an16:1 LVCMOS/LVTTL-to-
LVPECL/ LVDS Clock Multiplexer which can operate
HiPerClockS™
up to 250MHz and is a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. Differential output levels can either be selected
to LVDS or LVPECL. The ICS859S1061I has 16 selectable
single-ended clock inputs. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The
CLK_SEL3 pin is the most significant bit and the binary number
applied to the select pins will select the same numbered data input
(i.e., 0000 selects CLK0).
ICS
Table 1A. V
CC_TAP
Function Table
Outputs
Q/nQ
LVPECL
LVPECL
LVDS
LVDS
Output Level Supply
2.5V
3.3V
2.5V
3.3V
V
CC_TAP
V
CC
V
CC
V
CC
Float
Table 1B. SEL_OUT Function Table
Input
SEL_OUT
1
0
Outputs
Q/nQ
LVPECL
LVDS
Block Diagram
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
CLK_SEL2
Pulldown
CLK_SEL3
Pulldown
CLK0
Pulldown
CLK1
Pulldown
Pin Assignment
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
V
CC_TAP
V
CC
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
CLK0
SEL_OUT
V
EE
Q
nQ
OE
nc
Q
nQ
CLK14
Pulldown
CLK15
Pulldown
ICS859S1061I
28-Lead TSSOP, 173MIL
4.4mm x 9.7mm x 0.925
mm
package body
G Package
Top View
OE
Pullup
SEL_OUT
Pullup
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice
.
IDT™ / ICS™
LVPECL/LVDS CLOCK MULTIPLEXER
1
ICS859S1601BGI REV. B JUNE 24, 2008
ICS859S1601I
1:16, LVCMOS/LVTTL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
Table 2. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11,
12.
13,
14
15
16
17, 18
19
20
21
22
23
24
25
26
27
28
Name
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
V
CC_TAP
V
CC
CLK_SEL0,
CLK_SEL1,
CLK_SEL2,
CLK_SEL3
nc
OE
nQ, Q
V
EE
SEL_OUT
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Input
Input
Input
Input
Input
Input
Input
Input
Power
Power
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Description
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Power supply pin. See Table 1A.
Power supply pin.
Input
Pulldown
Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
Unused
Input
Output
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
No connect.
Output enable pin for Q/nQ outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Negative supply pin.
Output select pin. When LOW, selects LVDS levels. When HIGH, selects
LVPECL levels. LVCMOS/LVTTL interface levels. See Table 1B.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
IDT™ / ICS™
LVPECL/LVDS CLOCK MULTIPLEXER
2
ICS859S1601BGI REV. B JUNE 24, 2008
ICS859S1601I
1:16, LVCMOS/LVTTL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
Table 3. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 4A. Clock Input Function Table
Inputs
CLK_SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLK_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLK_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLK_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
Q/nQ
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
Table 4B. Output Enable Function Table
Input
OE
1
0
Outputs
Q/nQ (default)
Clock stop, High/Low
IDT™ / ICS™
LVPECL/LVDS CLOCK MULTIPLEXER
3
ICS859S1601BGI REV. B JUNE 24, 2008
ICS859S1601I
1:16, LVCMOS/LVTTL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
10mA
15mA
77.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
40
Maximum
3.465
3.465
Units
V
V
mA
Table 5B. LVPECL Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
38
Maximum
2.625
2.625
Units
V
V
mA
Table 5C. LVDS Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
54
Maximum
3.465
Units
V
mA
IDT™ / ICS™
LVPECL/LVDS CLOCK MULTIPLEXER
4
ICS859S1601BGI REV. B JUNE 24, 2008
ICS859S1601I
1:16, LVCMOS/LVTTL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
PRELIMINARY
Table 5D. LVDS Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
51
Maximum
2.625
2.625
Units
V
V
mA
Table 5E. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
CLK[0:15],
CLK_SEL[0:3]
OE, SEL_OUT
Input
Low Current
CLK[0:15],
CLK_SEL[0:3]
OE, SEL_OUT
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
-10
Units
V
V
V
V
µA
µA
µA
µA
V
IL
I
IH
I
IL
Table 5F. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-peak Output Voltage Swing
Test Conditions
Minimum
Typical
V
CC
– 1.0
V
CC
– 1.4
0.6
Maximum
Units
µA
µA
V
NOTE 1: Outputs termination with 50
Ω
to V
CC
– 2V.
Table 5G. LVDS DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
Minimum
Typical
370
40
1.21
50
Maximum
Units
mV
mV
V
mV
IDT™ / ICS™
LVPECL/LVDS CLOCK MULTIPLEXER
5
ICS859S1601BGI REV. B JUNE 24, 2008
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