Si53304
1:6 L
OW
J
I T T E R
U
NIVERSAL
B
U F F E R
/L
EVEL
T
RANSLATOR WITH
2 : 1 I
NPUT
M
UX A N D
I
NDIVIDUAL
OE
Features
6 differential or 12 LVCMOS outputs
Ultra-low additive jitter: 45 fs rms
Wide frequency range: 1 to 725 MHz
Any-format input with pin selectable
output formats: LVPECL, Low Power
LVPECL, LVDS, CML, HCSL,
LVCMOS
2:1 mux with hot-swappable inputs
Glitchless input clock switching
Synchronous output enable
Individual output enable
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
1.2/1.5 V LVCMOS output support
Excellent power supply noise
rejection (PSRR)
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 32-QFN (5x5 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Applications
Ordering Information:
See page 28.
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Pin Assignments
Si53304
Description
Q1
Q1
Q2
Q2
Q3
Q3
Q4
26
OE
1
OE
2
OE
3
CLK0
CLK0
CLK1
Functional Block Diagram
VDD
VDDO
A
SFOUT
A
[1:0]
OE[2:0]
Patents pending
V
REF
Vref
Generator
Power
Supply
Filtering
CLK0
BANK A
/CLK0
VDDO
B
SFOUT
B
[1:0]
OE[5:3]
CLK1
/CLK1
CLK_SEL
Switching
Logic
BANK B
Rev. 1.0 4/14
Copyright © 2014 by Silicon Laboratories
CLK1
OE
4
The Si53304 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53304 features a 2:1 mux with
glitchless switching, making it ideal for redundant clocking applications. The
Si53304 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53304 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Q4
25
32
31
30
29
28
27
OE
0
SFOUT
A
[1]
SFOUT
A
[0]
Q0
Q0
GND
V
DD
CLK_SEL
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
9
GND
PAD
24
23
22
21
20
19
18
17
OE
5
SFOUT
B
[1]
SFOUT
B
[0]
Q5
Q5
V
DDOB
V
DDOA
V
REF
Si53304
Si53304
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Input Clock Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8. Power Supply (V
DD
and V
DDOX
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1. Si53304 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2
Rev. 1.0
Si53304
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T
A
V
DD
LVDS, CML
Test Condition
Min
–40
1.71
2.38
2.97
LVPECL, low power LVPECL,
LVCMOS
HCSL
Output Buffer Supply
Voltage*
V
DDOX
LVDS, CML, LVCMOS
2.38
2.97
2.97
1.71
2.38
2.97
LVPECL, low power LVPECL
2.38
2.97
HCSL
2.97
Typ
—
1.8
2.5
3.3
2.5
3.3
3.3
1.8
2.5
3.3
2.5
3.3
3.3
Max
85
1.89
2.63
3.63
2.63
3.63
3.63
1.89
2.63
3.63
2.63
3.63
3.63
Unit
°C
V
V
V
V
V
V
V
V
V
V
V
V
*Note:
Core supply V
DD
and output buffer supplies V
DDO
are independent. LVCMOS clock input is not supported for
V
DD
=
1.8V but is supported for LVCMOS clock output for
V
DDOX
= 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.9.1. LVCMOS Output Termination To Support 1.5V and 1.2V”
Table 2. Input Clock Specifications
(V
DD
=1.8 V
5%, 2.5 V
5%, or 3.3 V
10%, T
A
=–40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High Volt-
age
LVCMOS Input Low Volt-
age
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK0 and CLK1 pins with
respect to GND
Test Condition
V
DD
= 2.5 V
5%, 3.3 V
10%
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x
0.3
—
Unit
V
V
V
V
pF
Rev. 1.0
3
Si53304
Table 3. DC Common Characteristics
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz (diff)
@200 MHz (CMOS)
Symbol
I
DD
I
DDOX
Test Condition
Min
—
Typ
65
35
35
20
35
35
5
8
15
VDD/2
—
0.5 x
VDD
—
25
25
Max
100
—
—
—
—
—
—
—
—
—
—
0.55 x
VDD
0.2 x
VDD
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
k
k
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)*
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load (3.3 V)
CMOS (1.8 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (2.5 V, SFOUT = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, C
L
= 5 pF, 200 MHz
—
—
—
—
—
—
—
—
—
0.8 x
VDD
0.45 x
VDD
—
—
—
Input Clock Voltage
Reference
Input High Voltage
Input Mid Voltage
Input Low Voltage
Internal Pull-down
Resistor
Internal Pull-up
Resistor
V
REF
V
IH
V
IM
V
IL
R
DOWN
R
UP
V
REF
pin
I
REF
= +/-500
A
SFOUTx,
CLK_SEL, OEx
SFOUTx,
3-level input pins
SFOUTx,
CLK_SEL, OEx
CLK_SEL, SFOUTx
OEx, SFOUTx
*Note:
Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.
4
Rev. 1.0
Si53304
Table 4. Output Characteristics (LVPECL)
(V
DDOX
= 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Output DC Common Mode
Voltage
Single-Ended
Output Swing*
Symbol
V
COM
V
SE
Test Condition
Min
V
DDOX
– 1.595
0.55
Typ
—
0.80
Max
V
DDOX
– 1.245
1.050
Unit
V
V
*Note:
Unused outputs can be left floating. Do not short unused outputs to ground.
Table 5. Output Characteristics (Low Power LVPECL)
(V
DDOX
= 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Output DC Common
Mode Voltage
Single-Ended
Output Swing
Symbol
V
COM
V
SE
Test Condition
R
L
= 100
across
Qn and Qn
R
L
= 100
across
Qn and Qn
Min
V
DDOX
– 1.895
0.25
Typ
Max
V
DDOX
– 1.275
Unit
V
V
0.60
0.85
Table 6. Output Characteristics—CML
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
V
SE
Test Condition
Terminated as shown in Figure 9
(CML termination).
Min
300
Typ
400
Max
550
Unit
mV
Table 7. Output Characteristics—LVDS
(V
DDOX
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(V
DDO
= 2.5 V or
3.3V)
Output Common
Mode Voltage
(V
DDO
= 1.8 V)
Symbol
V
SE
V
COM1
Test Condition
R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 2.38 to 2.63 V, 2.97 to
3.63 V, R
L
= 100
Ω
across Q
N
and Q
N
V
DDOX
= 1.71 to 1.89 V,
R
L
= 100
Ω
across Q
N
and Q
N
Min
247
1.10
Typ
—
1.25
Max
490
1.35
Unit
mV
V
V
COM2
0.85
0.97
1.25
V
Rev. 1.0
5
stm32/stm8
京公网安备 11010802033920号
EEWORLD
