EEWORLDEEWORLDEEWORLD

Part Number

Search

8N4Q001EG-0061CDI8

Description
IC osc clock QD freq 10clcc
Categorysemiconductor    Analog mixed-signal IC   
File Size163KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

8N4Q001EG-0061CDI8 Online Shopping

Suppliers Part Number Price MOQ In stock  
8N4Q001EG-0061CDI8 - - View Buy Now

8N4Q001EG-0061CDI8 Overview

IC osc clock QD freq 10clcc

Quad-Frequency Programmable XO IDT8N4Q001 REV G
DATA SHEET
General Description
The IDT8N4Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4Q001 can be programmed via the I
2
C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷
N
(N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to four
independent PLL divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency and
internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVDS clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps
(typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps
(typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
f
XTAL
÷MINT,
MFRAC
2
25
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
DNU 1
OE 2
GND 3
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
8 V
DD
7 nQ
6 Q
7
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
IDT8N4Q001
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
1
©2012 Integrated Device Technology, Inc.
Is it necessary to use exhaust cleaner on new cars?
Exhaust cleaner is a new fuel additive in recent years, especially in some auto repair shops, 4S stores, etc. You can see the shadow of exhaust cleaner. Sometimes at gas stations, you can meet staff w...
paoniu Automotive Electronics
Questions about STM32 and STR912FFT
Can an expert tell me if the FFT in the DSP library under STM32 can be directly ported to STR912?How to get the FFT-table in the .s file? Forexample:TableFFT_V7; N=16DCW 0x4000,0x0000, 0x4000,0x0000, ...
mengzhong163 stm32/stm8
msOS
Upload the msOS I've been playing with recently. It feels very interesting. You can play with 51. It's suitable for embedded entry and helps to understand basic concepts. The function pointers and str...
dj狂人 Embedded System
【Book Collection】Electromagnetic Field Integral Equation Method
[b]Contents: [/b] Introduction Chapter 1 Integral Expression of Electromagnetic Field Chapter 2 Integral Method of Current Field Quantities Chapter 3 Magnetization of Matter and Its Field Quantities C...
wzt RF/Wirelessly
Looking for 51 single chip microcomputer programmer and emulator
Does anyone have a 51 MCU programmer and simulator, or a schematic diagram? The ones sold in the market are too expensive, and I don't have the money. I want to make one myself, but I don't have a sch...
benf Embedded System
Purgatory Legend - Any Frequency Division Battle
Frequency division has always played an important role in the design of FPGA. When it comes to frequency division, I believe many people have thought of using a calculator to calculate the desired clo...
梦翼师兄 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1834  2234  1849  1299  2576  37  45  38  27  52 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号