NPCT420CA0WX datasheet, PDF - EEWORLD Datasheet

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NPCT420CA0WX: DescriptionIC tpm safekeeper; CategoryThe embedded processor and controller Microcontrollers and processors; File Size285KB，25 Pages; ManufacturerNuvoton Technology Corporation; Websitehttp://www.nuvoton.com.cn/hq/

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NPCT420CA0WX Overview

IC tpm safekeeper

NPCT420CA0WX Parametric

Parameter Name	Attribute value
Maker	Nuvoton Technology Corporation
package instruction	TSSOP-28
Reach Compliance Code	compliant
JESD-30 code	R-PDSO-G28
length	9.7 mm
Number of terminals	28
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Maximum seat height	1.2 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT

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NPCT42x Trusted Platform Module (TPM)

Preliminary

March 2011

Revision 1.1

NPCT42x Trusted Platform Module (TPM)

General Description

The NPCT42x single-chip Trusted Platform Module (TPM) is

a family of third-generation, Nuvoton SafeKeeper technolo-

gy devices. The devices implement the Trusted Computing

Group (TCG) version 1.2 specifications for PC-Client TPM.

The NPCT42x devices are designed to reduce system boot

time and Trusted OS loading time. They provide a solution

for PC security for a wide range of PC applications.

The NPCT42x family of devices are

compliant and are supported by Linux kernel v2.6.18 and

higher.

Microsoft



Windows



Bus Interface

■

LPC Bus Interface

—

Based on Intel’s

LPC Interface Specification Revi-

sion 1.1, August 2002

—

TPM 1.2 Interface (TIS)

Clocking and Supply

■

On-Chip Clock Generator

Power Supply

—

3.3V supply operation

—

Separate pins for main (V

) and standby (V

)

power supplies

—

Low standby power consumption

Features

General

■

Single-chip TPM solution

—

No external parts required

Compatible with

TPM Main Specification Version 1.2

Revision 116

and

PC Client Specific TPM Interface

Specification Version 1.21 Revision 72

Host Interface

—

TPM 1.2 standard interface (TIS) with five localities

—

Supports legacy locality by using TIS protocol with

I/O mapped registers

Secure General-Purpose I/O (GPIO)

—

Five GPIO pins

—

I/O pins individually configured as input or output

—

Configurable internal pull-up resistors

—

TCG 1.2-defined interface

—

Dedicated Physical Presence (PP) pin with config-

urable pull-up or pull-down resistor

Tick Counter

Software

■

TPM BIOS drivers: Memory Absent (MA) and Memory

Present (MP)

TPM Device Driver for Microsoft Windows

NTRU Cryptosystems (acquired by Security Innova-

tion



) Core TCG Software Stack (CTSS)

Wave Systems Cryptographic Service Provider (CSP)

with either EMBASSY

Security Center (ESC) or

EMBASSY Trust Suite (ETS) OEM Edition

■

System Block Diagram

Chipset

LPC Bus

Physical

Presence

NPCT42x

SuperI/O

GPIO

www.nuvoton.com

NPCT42x

Table of Contents

Features.............................................................................................................................................................. 1

Product-Specific Information............................................................................................................................... 2

Datasheet Revision Record ............................................................................................................................... 3

1.0

Signal/Pin Connection and Description

1.1

1.2

1.3

CONNECTION DIAGRAM ........................................................................................................... 6

BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 6

SIGNAL/PIN DESCRIPTIONS ..................................................................................................... 7

1.3.1

LPC Interface ................................................................................................................. 7

1.3.2

Inputs and Outputs ....................................................................................................... 7

1.3.3

Configuration Straps and Testing .................................................................................. 7

1.3.4

Power and Ground ........................................................................................................ 8

1.3.5

Not Connected ............................................................................................................... 8

INTERNAL PULL-UP AND PULL-DOWN RESISTORS .............................................................. 8

1.4

2.0

Trusted Platform Module (TPM) Overview

2.1

2.2

2.3

SYSTEM CONNECTIONS .......................................................................................................... 9

POWER MANAGEMENT (PM) .................................................................................................... 9

HOST INTERFACE ..................................................................................................................... 9

3.0

I/O Configuration Registers

3.1

CONFIGURATION REGISTER STRUCTURE AND ACCESS .................................................. 10

3.1.1

The Index-Data Register Pair ...................................................................................... 10

3.1.2

TPM Configuration Records ........................................................................................ 10

3.1.3

Reset Configuration Setup .......................................................................................... 11

3.1.4

4.0

TPM Host Interface

4.1

TPM INTERFACE MODULE (TIS) ............................................................................................ 12

4.1.1

Features ...................................................................................................................... 12

4.1.2

Host Interrupt Support ................................................................................................. 12

4.1.3

Host TPM Legacy Interface Registers ......................................................................... 12

5.0

Device Specifications

5.1

GENERAL DC ELECTRICAL CHARACTERISTICS ................................................................. 13

5.1.1

Recommended Operating Conditions ......................................................................... 13

5.1.2

Absolute Maximum Ratings ......................................................................................... 13

5.1.3

Capacitance ................................................................................................................ 13

5.1.4

Power Consumption under Recommended Operating Conditions .............................. 14

DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES ................................................... 15

5.2.1

Input, TTL Compatible ................................................................................................. 15

5.2.2

Input, TTL Compatible, with Schmitt Trigger ............................................................... 15

5.2.3

Input, PCI 3.3V Compatible ......................................................................................... 15

5.2.4

Output, TTL/CMOS Compatible, Push-Pull Buffer ...................................................... 16

5.2.5

Output, Open Drain Buffer ........................................................................................... 16

5.2.6

Output, PCI 3.3V Compatible ...................................................................................... 16

Revision 1.1

5.2

www.nuvoton.com

NPCT420CA0WX Related Products

	NPCT420CA0WX	NPCT420AA0WX	NPCT420BA0WX	NPCT420DA0WX
Description	IC tpm safekeeper	IC tpm safekeeper	IC tpm safekeeper	IC tpm safekeeper

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