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SY100EL15LZI TR

Description
IC clk buffer 2:4 16soic
Categorysemiconductor    Analog mixed-signal IC   
File Size56KB,5 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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SY100EL15LZI TR Overview

IC clk buffer 2:4 16soic

Micrel, Inc.
3.3V 1:4 CLOCK
DISTRIBUTION
Precision Edge
®
SY100EL15L
Precision Edge
®
SY100EL15L
FEATURES
s
3.3V power supply
s
50ps output-to-output skew
s
Low power
s
Synchronous enable/disable
s
Multiplexed clock input
s
75K
internal input pull-down resistors
s
Available in 16-pin SOIC package
Precision Edge
®
DESCRIPTION
The SY100EL15L is a low skew 1:4 clock distribution
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
BB
output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to V
EE
and CLK input will bias around
V
CC
/2.
PIN NAMES
Pin
CLK
SCLK
EN
SEL
V
BB
Q
0-3
Function
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output
Differential Clock Outputs
TRUTH TABLE
CLK
L
H
X
X
X
SCLK
X
X
L
H
X
SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
* On next negative transition of CLK or SCLK
Precision Edge is a registered trademark of Micrel, Inc.
M9999-031306
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
1
Issue Date: March 2006

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Description IC clk buffer 2:4 16soic IC clk buffer 2:4 16soic IC CLK BUFFER 2:4 16SOIC IC CLK BUFFER 2:4 16SOIC
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