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RD38F1020W0YTQ0SB93

Description
IC flash 32mbit 65ns 66scsp
Categorystorage   
File Size327KB,22 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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RD38F1020W0YTQ0SB93 Overview

IC flash 32mbit 65ns 66scsp

Intel
®
Wireless Flash Memory (W18
SCSP)
32-Mbit W18 + 8-Mbit SRAM (38F1020W0YTQ0, 38F1020W0YBQ0)
Datasheet
Product Features
Flash Architecture
— Flexible, Multi-Partition, Dual-Operation:
Read-While-Write / Read-While-Erase
— 8 Partitions, 4 Mbits each
— 7 Main Partitions, 8 Main Blocks each
— 1 Parameter Partition, 8 Parameter + 7 Main
Blocks
— 32-KWord Main Blocks, 4-KWord
Parameter Blocks
— Top and Bottom Parameter Configuration
Flash Automation Suspend Operations
— Erase Suspend to Program or Read
— Program Suspend to Read
— 5 µs (typ) Program/Erase Suspend Latency
Flash Software
— Intel
®
Flash Data Integrator (Intel
®
FDI)
Optimized
— Common Flash Interface (CFI)
— 32-Mbit Flash die + 8-Mbit SRAM die
— Reduces Board Space Requirement
— Simplifies PCB Design Complexity
— Easy Migration to Future SCSP Devices
SCSP Architecture
Flash Performance
— 65 ns Initial Access Speed
— 25 ns Page-Mode Read Speed; 4-Word Page
— 14 ns Burst-Mode Read Speed
— 4-, 8-, 16- or Continuous-Word Burst Modes
— Burst- and Page-Mode Reads in Parameter
and Main Partitions
— Burst Suspend
— Burst-Mode Reads can Traverse Partition
Boundaries
— Programmable WAIT Polarity
— Enhanced Factory Programming: 3.1 µs/
Word (typ)
SCSP Voltage
— 1.7 V to 1.95 V V
CC
/V
CCQ
and S-V
CC
SCSP Packaging
— 0.8 mm Ball-Pitch Intel
®
SCSP
— Area: 8x10 mm, Height: 1.2 mm max
— 88-Ball (8 x 10 Matrix): 80 Active Balls with
2 Support Balls at Each Corner
— 70 ns Access Time
— Low-Voltage Data Retention Mode
SRAM Architecture and Performance
Flash Quality and Reliability
— Extended Temperature: –25 °C to +85 °C
— Minimum 100,000 Block Erase Cycles
— Intel
®
0.13 µm ETOX
TM
VIII Process
Technology
Flash Data Protection
— Absolute Protection with VPP and WP#
— Individual Dynamic Zero-Latency Block
Locking
— Individual Block Lock-Down
— Erase/Program Lockout during Power
Transitions
Flash Protection Register
— 64 Unique Device Identifier Bits
— 64 User-Programmable OTP Bits
By stacking the Intel
®
Wireless Flash Memory (W18) device in combination with a low-power
8-Mbit SRAM device, a versatile and compact Stacked Chip Scale Package (SCSP) provides a
solution for high-performance, low-power, board-constrained memory applications. This
datasheet describes the key features of this 32-Mbit W18 + 8-Mbit SRAM combination device.
Refer to the latest revision of the
Intel
®
Wireless Flash Memory (W18) Datasheet
(order number
290701) for flash device details not provided in this document.
Notice:
This document contains information available at the time of its release. The specifica-
tions are subject to change without notice. Verify with your local Intel sales office that you have
the latest datasheet before finalizing a design.
252635-002
May 2004

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