SY89537LMG TR datasheet, PDF - EEWORLD Datasheet

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SY89537LMG TR: DescriptionIC synthesizr lvpecl/lvds 44-mlf; Categorysemiconductor Analog mixed-signal IC; File Size744KB，19 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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SY89537LMG TR Overview

IC synthesizr lvpecl/lvds 44-mlf

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SY89537L

3.3V Precision LVPECL and LVDS

Programmable Multiple Output Bank Clock

Synthesizer and Fanout Buffer

General Description

The SY89537L integrated programmable clock

synthesizer and fanout is part of a precision PLL-

based clock generation family optimized for enterprise

switch, router, and multiprocessor server applications.

This family is ideal for generating internal system

timing requirements up to 700MHz for multiple ASICs,

FPGAs, and NPUs. These devices integrate the

following blocks into a single monolithic IC:

•

PLL (Phase-Lock-Loop) based synthesizer

Fanout buffers

Clock generator (dividers)

Logic translation (LVPECL, LVDS)

Precision Edge

Features

•

Integrated programmable synthesizer with multiple

output dividers, fanout buffers, and clock drivers

•

Direct interface to crystal: 14MHz to 18MHz

•

Input MUX accepts a reference and a crystal

(XTAL) source

– Ideal for reference backup clock source or

system test frequency source

– Patent-pending unique input MUX isolates XTAL

and reference inputs minimizes crosstalk

•

Guaranteed AC performance:

– 87.15MHz to 700MHz output frequency range

(with RFCK at 16.6MHz)

– <100ps

total jitter

– <7ps

RMS

cycle-to-cycle jitter

– <8ps

deterministic jitter

– <0.7ps

RMS

crosstalk induced jitter

– <50ps bank-to-bank skew

•

Output bank synchronization control pin

•

LVPECL and LVDS outputs

•

TTL/CMOS compatible control logic

•

Five independently programmable output

frequency banks:

– Four differential LVPECL output banks

– One differential LVDS output bank with 3 output

pairs

•

Separate output enable for each bank

•

3.3V ±10% power supply (2.5V output capable)

•

Guaranteed over the commercial and industrial

temperature range (-40C to +85C)

•

Available in 44-pin (7mm x 7mm) QFN package

Five independently programmable output

banks

This level of integration minimizes additive jitter and

part-to-part skew associated with discrete alternatives,

resulting in superior system-level timing with reduced

board space and power. For applications that require

a zero-delay function, see the SY89538L.

All support documentation can be found on

Micrel’s web site at:

www.micrel.com.

Applications

•

Enterprise routers, switches, servers and

workstations

•

Parallel processor-based systems

•

Internal system clock generation for ASICs, NPUs,

FPGAs

Markets

•

LAN/WAN

•

Enterprise servers

•

Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

December 2007

M9999-121207-B

hbwhelp@micrel.com

or (408) 955-1690

Micrel, Inc.

SY89537L

Pin Description

Power

Pin Number

Pin Name

VCCA

VCCD

Pin Function

Analog PLL Power Pin: Connects to “quiet” 3.3V supply. 3.3V power pins are not internally

connected on the die, and must be connected together on the PCB. Bypass with

0.1µF//0.01µF low ESR capacitors and place as close to the VCCA pin as possible.

Digital Logic Core Power Pin: VCCD connects to a 3.3V supply. Power pins are not internally

connected on the die, and must be connected together on the PCB. Bypass with

0.1µF//0.01µF low ESR capacitors and place bypass capacitors as close to the VCCD pin as

possible.

LVDS and LVPECL Output Driver Power Pins: The outputs can be powered from a 2.5V

supply or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or 2.5V

±5%. Power pins are not internally connected on the die, and must be connected together on

the PCB. Bypass with 0.1µF//0.01µF low ESR capacitor and place as close to the VCCO pin

as possible.

PLL Ground: Connect to “quiet” ground. GNDA and GND are not internally connected on the

die, and must be connected on the PCB.

Ground: GND pins and exposed pad must both be connected to the most negative potential

of the chip ground.

14, 27, 30, 36

VCCO

11, 21, 22

GNDA

GND,

Exposed Pad

Control and Configuration

Pin Number

2, 4

Pin Name

RSEL1, RSEL0

Pin Function

Analog Input/Output: Provides the reference voltage for the PLL loop filter and is used with the

LF pin. See "External Loop Filter Considerations" for recommended loop filter values.

Analog Input/Output: Provides the loop filter node for the PLL. See “External Loop Filter

Considerations” for loop filter values.

TTL/CMOS Reference Input Pre-scaler. The two-bit input pre-scaler divides the input

reference frequency by /1, /2, /4, or /8. RSEL0 is the LSB bit. See "Reference Input Divider

Select Table," for proper decoding. The threshold voltage V

= V

/2. Internal 25kΩ pull-up.

TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input. Internal

25kΩ pull-up. The default is logic HIGH, and selects the XTAL input. The threshold voltage V

= V

/2.

Logic HIGH: XTAL Select

Logic LOW: Reference Input Select

TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL and LEN

are used to decode the selection and the post divider of the LVDS output bank. LSEL includes

an internal 25kΩ pull-up. See “LVDS Output and Frequency Select Table” for proper decoding.

The threshold voltage V

= V

/2.

TTL/CMOS Input Enable Pin. Used to control the LOUT0-LOUT2 outputs and acts as a

frequency select pin. LEN and LSEL are used to decode the selection and the post divider of

the LVDS output bank. See the “LVDS Output and Frequency Select Table” for proper

decoding. LEN includes an internal 25kΩ pull-up. When disabled, LOUT0-LOUT2 outputs are

LOW, and the complimentary outputs are HIGH. The threshold voltage V

= V

/2.

TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx and

PENx are used together to decode the selection and post divider of the PECL outputs. PSELx

pins include an internal 25kΩ pull-up. The threshold voltage V

= V

/2. See "PECL Output

Frequency and Select Table" for proper decoding.

TTL/CMOS input enable pin. Used to control the POUT0-PECL2 outputs and acts as a

frequency select pins. PENx and PSELx are used together; see the “PECL Output and

Frequency Select Table” for proper decoding. PENx includes an internal 25kΩ pull-up. When

disabled, PECL0-PECL2 outputs are LOW. The threshold voltage V

= V

/2.

TTL/CMOS output bank synchronization control. Internal 25kΩ pull-up. The default state is

HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized

when the SYNC control pin is toggled with a HIGH-LOW-HIGH transition. See

“Synchronization” section for details. The threshold voltage V

= V

/2.

INSEL

LSEL

LEN

PSEL0

PSEL1

PSEL2

PSEL3

PEN0

PEN1

PEN2

PEN3

SYNC

December 2007

M9999-121207-B

hbwhelp@micrel.com

or (408) 955-1690

SY89537LMG TR Related Products

	SY89537LMG TR	SY89537LMH TR	SY89537LMH	SY89537LMZTR
Description	IC synthesizr lvpecl/lvds 44-mlf	IC synthesizr lvpecl/lvds 44-mlf	IC synthesizr lvpecl/lvds 44-mlf	756MHz, OTHER CLOCK GENERATOR, QCC44, 7 X 7 MM, MO-220, MLF-44

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