Freescale Semiconductor, Inc.
µ MOTOROLA
Freescale Semiconductor, Inc...
M68040 User’s Manual
Including the
MC68040,
MC68040V,
MC68LC040,
MC68EC040,
and
MC68EC040V
©MOTOROLA INC., 1990
Revised 1992, 1993
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
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fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and the
are registered trademarks of Motorola, Inc. Motorola, Inc. is an
Equal Opportunity/Affirmative Action Employer.
©MOTOROLA INC., 1992
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PREFACE
The complete documentation package for the MC68040, MC68040V, MC68LC040,
MC68EC040, and MC68EC040V (collectively called M68040) consists of the
M68040UM/AD,
M68040 User’s Manual
, and the M68000PM/AD,
M68000 Family
Programmer’s Reference Manual.
The
M68040 User’s Manual
describes the capabilities,
operation, and programming of the M68040 32-bit third-generation microprocessors. The
M68000 Family Programmer’s Reference Manual
contains the complete instruction set for
the M68000 family.
The introduction of this manual includes general information concerning the MC68040 and
summarizes the differences between the M68040 member devices. Additionally, three
appendices provide detailed information on how these M68040 dirivatives operate
differently from the MC68040. For detailed information on one of these M68040
dirivatives, use the following table to determine which appendices to read in conjunction
with the rest of this manual.
Device Number
MC68040V
MC68LC040
MC68EC040
MC68EC040V
Appendices
Appendix A MC68LC040
and
Appendix C MC68040V and MC68EC040V
Appendix A MC68LC040
Appendix B MC68EC040
Appendix B MC68EC040
and
Appendix C MC68040V and MC68EC040V
Freescale Semiconductor, Inc...
When reading this manual,
remember
to disregard information concerning floating-point
in reference to the MC68040V and MC68LC040, and to disregard information concerning
floating-point and memory management in reference to the MC68EC040 and
MC68EC040V. The organization of this manual is as follows:
Section 1
Section 2
Section 3
Section 4
Section 5
Section 6
Section 7
Section 8
Section 9
Section 10
Section 11
Section 12
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Index
iv
Introduction
Integer Unit
Memory Management Unit (Except MC68EC040 and MC68EC040V)
Instruction and Data Caches
Signal Description
IEEE 1149.1 Test Access Port (JTAG)
Bus Operation
Exception Processing
Floating-Point Unit (MC68040)
Instruction Timings
MC68040 Electrical and Thermal Characteristics
Ordering Information and Mechanical Data
MC68LC040
MC68EC040
MC68040V and MC68EC040V
M68000 Family Summary
Floating-Point Emulation (M68040FPSP)
M68040 USER’S MANUAL
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MOTOROLA
Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Paragraph
Number
Title
Section 1
Introduction
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
Differences ............................................................................................ 1-1
MC68040V and MC68LC040 ............................................................ 1-1
MC68EC040 and MC68EC040V ....................................................... 1-2
Features ................................................................................................ 1-3
Extensions to the M68000 Family ......................................................... 1-3
Functional Blocks .................................................................................. 1-3
Processing States ................................................................................. 1-5
Programming Model .............................................................................. 1-5
Data Format Summary.......................................................................... 1-9
Addressing Capabilities Summary ........................................................ 1-9
Notational Conventions ......................................................................... 1-11
Instruction Set Overview ....................................................................... 1-13
Section 2
Integer Unit
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
Integer Unit Pipeline.............................................................................. 2-1
Integer Unit Register Description .......................................................... 2-4
Integer Unit User Programming Model .............................................. 2-4
Data Registers (D7–D0) ................................................................ 2-4
Address Registers (A6–A0) ........................................................... 2-4
System Stack Pointer (A7) ............................................................. 2-5
Program Counter ........................................................................... 2-5
Condition Code Register ................................................................ 2-5
Integer Unit Supervisor Programming Model .................................... 2-5
Interrupt and Master Stack Pointers .............................................. 2-6
Status Register .............................................................................. 2-7
Vector Base Register ..................................................................... 2-7
Alternate Function Code Registers ................................................ 2-7
Cache Control Register ................................................................. 2-8
Page
Number
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vi
M68040 USER’S MANUAL
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
Section 3
Memory Management Unit
(Except MC68EC040 and MC68EC040V)
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.3
3.2.4
3.2.4.1
3.2.4.2
3.2.4.3
3.2.4.4
3.2.5
3.2.6
3.2.6.1
3.2.6.2
3.2.6.3
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.3
3.7.4
Memory Management Programming Model .......................................... 3-3
User and Supervisor Root Pointer Registers..................................... 3-3
Translation Control Register .............................................................. 3-4
Transparent Translation Registers .................................................... 3-5
MMU Status Register ........................................................................ 3-6
Logical Address Translation .................................................................. 3-7
Translation Tables ............................................................................. 3-7
Descriptors ........................................................................................ 3-12
Table Descriptors ........................................................................... 3-12
Page Descriptors ........................................................................... 3-13
Descriptor Field Definitions ............................................................ 3-13
Translation Table Example ................................................................ 3-16
Variations in Translation Table Structure .......................................... 3-16
Indirect Action ................................................................................ 3-16
Table Sharing Between Tasks ....................................................... 3-18
Table Paging .................................................................................. 3-19
Dynamically Allocated Tables ........................................................ 3-21
Table Search Accesses ..................................................................... 3-21
Address Translation Protection ......................................................... 3-23
Supervisor and User Translation Tables........................................ 3-23
Supervisor Only.............................................................................. 3-23
Write Protect .................................................................................. 3-24
Address Translation Caches ................................................................. 3-26
Transparent Translation ........................................................................ 3-29
Address Translation Summary .............................................................. 3-30
MMU Effect on
RSTI
and
MDIS
............................................................. 3-31
Effect of
RSTI
on the MMUs .............................................................. 3-31
Effect of
MDIS
on Address Translation .............................................. 3-31
MMU Instructions .................................................................................. 3-33
MOVEC ............................................................................................. 3-33
PFLUSH............................................................................................. 3-33
PTEST ............................................................................................... 3-33
Register Programming Considerations.............................................. 3-34
Page
Number
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M68040 USER’S MANUAL
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