[i=s]This post was last edited by 285062025 on 2014-10-16 15:42[/i] The program for writing the timing of the control lines SPI_CS SPI_CLK SPI_MOSI connected to ADF4158 for debugging ADF5148 is: void ...
I am currently using FPGA to do network experiments and testing the performance of lwip in raw mode.
S3e 500 board, mb core + xilkernel4.0 + lwip130, has been tuned, ping function, tcp and udp data tr...
There are not three phase-locked loops? The hint is that there are two, and there are only two input clocks, so two phase-locked loops are used, and the other one is not used?...
[font=宋体][size=2]The previous post released the first version of MsgOS source code and a brief introduction. [/size][/font][url=https://bbs.eeworld.com.cn/thread-492496-1-1.html]https://bbs.eeworld.co...
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Limited vocabulary recognition
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