TC7WT74FU
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7WT74FU
D-Type Flip-Flop with Preset and Clear
The TC7WT74FU is high speed CMOS D-TYPE FLIP-FLOP fabricated
with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent Bipolar
schottky TTL while maintaining the CMOS low power dissipation.
The input threshold levels are compatible with TTL output voltage.
The signal level applied to the D-INPUT is tranceferred to
Q-OUTPUT during the positive going trasition of the CK pulse.
CLEAR and PRESET are independent of the CK and are
accompished by setting the appropriate input low.
All inputs are equipped with protection circuits against static
dichage or transient excess voltage.
TC7WT74FU
(SM8)
Features
•
•
•
•
•
High speed: f
MAX = 53 MHz(typ.) at
V
CC
= 5 V
Low power dissipation: I
CC =
2
μA
(max) at Ta = 25°C
Compatible with TTL inputs: V
IL =
0.8 V(max) at Ta=25°C
Output drive capability: 10 LSTTL Loads
Symmetrical output impedance: |I
OH
| = I
OL
= 4 mA (min)
Weight
SSOP8-P-0.65: 0.02 g (typ.)
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Lead temperature (10s)
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
T
L
Rating
−0.5
to 7
−0.5
to V
CC
+ 0.5
−0.5
to V
CC
+ 0.5
±20
±20
±25
±25
300
−65
to 150
260
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
Marking
Type name
WT74
Lot No.
Pin Assignment
(top view)
CK 1
D 2
8 V
CC
7
PR
6 CLR
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in temperature,
etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating
temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba
Semiconductor Reliability Handbook (“Handling Precautions”/“Derating
Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Q
3
GND 4
5 Q
1
2009-01-22
Embedded System
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EEWORLD
