3F0
FS
VCCQ
REF
GND
TEST
2F1
09-0003
VCCN
FB
VCCN
2Q1
2Q0
3Q1
3Q0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Description
Features
• PI6C3Q99x family provides following products:
PI6C3Q991: 32-pin PLCC version
PI6C3Q993: 28-pin QSOP version
• Inputs are 5V Tolerant
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair; 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Input frequency: 3.75 MHz to 85 MHz
• Output frequency: 15 MHz to 85MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 3 skew grades:
PI6C3Q99x: t
SKEW0
<750ps
PI6C3Q99x-5: t
SKEW0
<500ps
PI6C3Q99x-2: t
SKEW0
<250ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: < 200ps peak-to-peak
• Industrial temperature range
• Packaging (Pb-free and Green available):
—32-pin PLCC
—28-pin QSOP
The PI6C3Q99x family is a 3.3V PLL-based clock driver intended for
high-performance computing and data-communication applica-
tions. A key feature of the programmable skew is the ability of
outputs to lead or lag the REF input signal. The PI6C3Q991 has 8
programmable skew outputs in 4 banks of 2, while the PI6C3Q993
has 6 programmable skew outputs and 2 zero skew outputs. Skew
is controlled by 3-level input signals that may be hard-wired to
appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held LOW, all outputs are synchronously
enabled. However, if GND/sOE is held HIGH, all outputs except 3Q0
and 3Q1 are synchronously disabled. Furthermore, when the V
CCQ
/PE is held HIGH, all outputs are synchronized with the positive
edge of the REF clock input. When V
CCQ
/PE is held LOW, all
outputs are synchronized with the negative edge of REF. Both
devices have LVTTL 12mA balanced drive outputs.
Pin Configurations
PI6C3Q991
REF
VCCQ
FS
PI6C3Q993
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
TEST
2F1
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
2Q0
2Q1
3F1
4F0
4F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
GND
4
5
6
7
8
9
10
11
12
13
14
3
2
1
32 31 30
29
28
27
26
25
24
23
22
15 16
21
17 18 19 20
2F0
GND/sOE
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
3F0
3F1
VCCQ/PE
VCCN
4Q1
4Q0
GND
3Q1
3Q0
VCCN
FB
1
PS8449H
10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Logic Block Diagrams
PI6C3Q991
GND/sOE
Skew
Select
3
V
CCQ
/PE
Skew
Select
REF
FB
3
FS
Skew
Select
3
3
4F1:0
3
PLL
Skew
Select
3
3
3F1:0
4Q0
4Q1
3
2F1:0
3Q0
3Q1
3
1F1:0
2Q0
2Q1
REF
FB
3
FS
PLL
Skew
Select
3
3
3F1:0
4Q0
4Q1
PI6C3Q993
GND/sOE
1Q0
1Q1
V
CCQ
/PE
Skew
Select
3
3
1F1:0
Skew
Select
3
3
2F1:0
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
Table 1. Pin Descriptions
Pin Name
REF
FB
TEST
(1)
Type
IN
IN
IN
Reference clock input
Feedback input
When TEST is held at MID level or HIGH level, the PLLi is disabled (except for conditions of Note 1). REF
goes to all outputs. Skew selections (see table 3) remain in effect. Set LOW for normal operation.
Synchronous output enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state -
3Q0 or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level
and GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] =
LL. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH outputs are synchronized with the
negative/positive edge of the reference clock.
3- level inputs for selecting 1 of 9 skew taps or frequency range.
Selects appropriate oscillator circuit based on anticipated frequency range. See Table 2
4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993 4Q[1:0] are fixed zero skew
outputs.
Functional De s cription
GND/sOE
(1)
IN
V
CCQ
/PE
nF [1:0]
FS
nQ [1:0]
V
CCN
V
CCQ
GND
IN
IN
IN
OUT
PWR Power supply for output buffers
PWR Power supply for phase locked loop and other internal circuitry
PWR Ground
Note:
1. When TEST = MID and GND/sOE = HIGH, the PLL remains active with nF[1:0] =LL functioning as an output disable control for the
individual output banks. See Table 3 for skew selections.
09-0003
2
PS8449H
10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Programmable Skew
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodate requirements for special timing relationships between
clocked components. Skew is selectable as a multiple of time units
- t
U
which is of the order of a nanosecond (see Table 2). There are
9 skew configurations available for each output pair. These configu-
rations are choosen by the nF[1:0] control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew
is not a requirement, the control pins can be left open for the zero skew
default setting. The skew selection Table (Table 3) shows how to
select specific skew taps by using the nF[1:0] control pins.
External Feedback
By providing external feedback, the PI6C3Q99X family gives users
flexibility with regard to skew adjustment. The FB signal is compared
with the input REF signal at the phase detector in order to drive the
V
CO
. Phase differences causes the V
CO
of the PLL to adjust up or
down accordingly. An internal loop filter moderates the response of
the V
CO
to the phase detector. The loop filter transfer function has
been chosen to provide minimal jitter (or frequency variation) while
still providing accurate responses to input frequency.
Table 2. PLL Programmable Skew Range and Resolution Table
FS = LOW
Timing unit calculatio n (t
U
)
V
CO
freq uency range (F
NOM
)
(2,3)
S kew ad justment range
(4)
Max. ad justment
Examp le 1, F
NOM
= 15 MHz
Examp le 2 , F
NOM
= 2 5 MHz
Examp le 3 , F
NOM
= 3 0 MHz
Examp le 4 , F
NOM
= 4 0 MHz
Examp le 5 , F
NOM
= 5 0 MHz
Examp le 6 , F
NOM
= 8 0 MHz
1/(4 4 xF
NOM
)
1 5 to 3 5 MHz
± 9 . 0 9 ns
± 49°
± 14%
t
U
= 1. 5 2 ns
t
U
= 0 . 9 1ns
t
U
= 0 . 7 6 ns
t
U
= 1. 5 4 ns
t
U
= 1. 2 8 ns
t
U
= 0 . 9 6 ns
t
U
= 0 . 7 7 ns
t
U
= 1. 5 6 ns
t
U
= 1. 2 5 ns
t
U
= 0 . 7 8 ns
FS = M ID
1/(2 6 xF
NOM
)
2 5 to 6 0 MHz
± 9 . 2 3 ns
± 83°
± 23%
FS = HIGH
1/(16 xF
NOM
)
4 0 to 8 5 MHz
± 9 . 3 8 ns
± 135°
± 37%
Notes:
2. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is
lowest.
3. The level on FS is determined by the nominal operating frequency of the V
CO
and Time Unit Generator. The V
CO
frequency appears at 1Q[1:0], 2Q[1:0], and the higher outputs when they are operated in undivided modes. The
frequency appearing at REF and FB inputs are the same as the V
CO
when the output is connected to FB undivided.
The frequency of the REF and FB inputs are 1/2 or 1/4 the V
CO
frequency when the part is configured for frequency
multiplication by using a divided output as the FB input.
4. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then
adjustment range greater. For example if a 4t
U
skewed output is used, all other outputs will be skewed by
–4t
U
in addition to whatever skew value is programmed for those outputs. Max adjustment range applies to output pairs
3 and 4 where ±6t
U
skew adjustment is possible and at the lowest F
NOM
value.
09-0003
3
PS8449H
10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Table 3. Skew Selection Table for Output Pairs
nF1:0
LL
(6)
LM
LH
ML
MM
MH
HL
HM
HH
Ske w (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero skew
+1t
U
+2t
U
+3t
U
+4t
U
Ske w (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero skew
+2t
U
+4t
U
+6t
U
Divide by 4
Ske w (Pair #4)
(5)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero skew
+2t
U
+4t
U
+6t
U
Inverted
(7)
Notes:
5. Programmable skew on pair #4 is not applicable for the PI6C3Q993.
6. LL disables outputs if TEST = MID level and GND/sOE = HIGH.
7. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when V
CCQ
/PE = HIGH, GND/sOE disables pair #4 LOW when
V
CCQ
/PE = LOW
Table 4. Absolute Maximum Ratings
Supply Voltage to Ground ...................................... –0.5V to 7.0V
Input Voltage .......................................................... –0.5V to 7.0V
Maximum Power Dissipation at T
A
= 85°C, PLCC ....... 0.80 watts
QSOP ....... 0.66 watts
T
STG
Storage Temperature .................................. –65°C to 150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the de-
vice at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Expo-
sure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
Table 5. Recommended Operating Range
S ymbo l
V
C C
T
A
D e s criptio n
P o wer S up p ly Vo ltage
Amb ient O p erating
Temp erature
PI6 C3 Q9 9 X/PI6 C3 Q9 9 X-5
(Indus tria l)
M in.
3.0
–40
M ax.
3.6
85
PI6 C3 Q9 9 X, PI6 C3 Q9 9 X-2 ,
PI6 C3 Q9 9 X-5
(Co mme rcia l)
M in.
3.0
0
M ax.
3.6
70
V
°C
Units
09-0003
4
PS8449H
10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock
®
Table 6. DC Characteristics Over Operating Range
S ymbo l
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Pa ra me te r
Inp ut HIGH Vo ltage
Inp ut LO W Vo ltage
Inp ut HIGH
Vo ltage
(8)
Te s t Co nditio n
Guaranteed Lo gic HIGH
(REF, F B inp uts o nly)
Guaranteed Lo gic LO W
(REF, F B inp uts o nly)
3 - Level Inp uts o nly
3 - Level Inp uts o nly
3 - Level Inp uts o nly
V
IN
= V
CC
o r GN D,
V
CC
= Max.
V
IN
= V
CC
o r GN D,
V
CC
= Max.
V
CC
= Max, V
IN
= GN D
HIGH level
MID Level
LO W Level
M in.
2.0
–0.5
V
CC
–0 . 6
V
CC
/2 –0 . 3 V
CC
/2 +0 . 3
0.6
5
200
50
200
100
100
2.2
0.55
V
M ax.
5.5
0.8
V
Units
Inp ut MID Vo ltage
(8)
Inp ut LO W Vo ltage
(8)
Inp ut Leakage C urrent
(REF, F B inp uts o nly)
3 - Level Inp ut DC C urrent
(TES T, F S , nF 1:0 )
Inp ut P ull- Up C urrent (V
CCQ
/P E)
I
3
I
PU
I
PD
V
OH
V
OL
uA
Inp ut P ull- Do wn C urrent (GN D/sO E) V
CC
= Max, V
IN
= V
CC
O utp ut HIGH Vo ltage
O utp ut LO W Vo ltage
V
CC
= Min, I
OH
= - 12 mA
V
CC
= Min, I
OL
= 12 mA
Table 7. Power Supply Characteristics
S y mbo l
I
CCQ
Δ
I
CCN
Pa ra me te r
Q uiescent P o wer S up p ly
C urrent
P o wer S up p ly C urrent p er
Inp ut HIGH
(9)
Dynamic P o wer S up p ly C urrent
p er O utp ut
(9)
To tal P o wer S up p ly C urrent
(9 )
To tal P o wer S up p ly C urrent
(9)
To tal P o wer S up p ly C urrent
(9)
Te s t Co nditio ns
V
CC =
Max, TES T = Mid . , REF = LO W,
GN D/sO E = LO W, All o utp uts unlo ad ed
V
CC
= Max V
IN
= 3 . 0 V
V
CC
= Max C
L
= 0 p F
V
CC
= 3 . 3 V, F
REF
= 2 0 MHz, C
L
=1 6 0 p F
(10)
V
CC
= 3 . 3 V, F
RE F
=3 3 MHz, C
L
=1 6 0 p F
(10)
V
CC
= 3 . 3 V, F
REF
=6 6 MHz, C
L
=1 6 0 p F
(10)
Ty p.
8.0
1.0
55
29
42
76
M ax.
15
30
125
Units
mA
μ
A
μ
A/
MHz
I
CCD
I
C
I
C
I
C
mA
Notes:
8. Inputs are wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
CC
/2. If inputs are switched, the
function and timing of the outputs may glitched, and the PLL may require additional time before datasheet specifications are achieved.
9. Guaranteed by characterization but not production tested.
10. For 8 outputs each loaded with C
L
= 20pF.
09-0003
5
PS8449H
10/27/09
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