PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Features
• PLL clock distribution optimized for SSTL_2 DDR SDRAM
applications.
• Distributes one differential clock input pair to five differential
clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the input clocks.
• Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
• Packaging (Pb-free & Green available):
– 28-pin TSSOP (L)
Description
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM
applications. This PLL Clock Buffer is designed for 2.5 V
DDQ
and
2.5V AV
DD
operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Analog Power input (AV
DD
). When the AV
DD
is strapped low, the
PLL is turned off and bypassed for test purposes.
The PI6CV855 is able to track Spread Spectrum Clocking to reduce
EMI.
Block Diagram
Pin Configuration
Y0
Y0
CLK
CLK
FBIN
FBIN
GND
Y0
Y0
VDDQ
CLK
CLK
AVDD
AGND
GND
Y1
Y1
VDDQ
Y2
Y2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
Y4
Y4
VDDQ
GND
FBOUT
FBOUT
VDDQ
FBIN
FBIN
GND
VDDQ
Y3
Y3
GND
Y1
Y1
PLL
Y2
Y2
Y3
Y3
Y4
28-Pin
L
23
22
21
20
19
18
17
16
15
AV
DD
Logic
and
Test Ciruit
Y4
FBOUT
FBOUT
08-0298
1
PS8545D
11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Pinout Table
Pin
Name
CLK
CLK
Y[0:4]
Y[0:4]
FBOUT
FBOUT
FBIN
FBIN
V
DDQ
AV
DD
AGND
GND
Pin No.
5
6
3,11,13,17,27
2,10,14,16,28
23
24
21
20
4,12,18,22,26
7
8
1,9,15,19,25
I
O
I/O
Type
I
Reference Clock input
Clock outputs.
Complement Clock outputs.
Feedback output, and Complement Feedback Output
Feedback input, and Complement Feedback input
Power Supply for I/O pins.
Power Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When
DD
AV
DD
is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.
Ground
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground for I/O pins.
De s cription
Function Table
Inputs
AV
DD
GND
GND
2.5V(nom)
2.5V(nom)
CLK
L
H
L
H
CLK
H
L
H
L
Y[0:4]
L
H
L
H
Y[0:4]
H
L
H
L
Outputs
FBOUT
L
H
L
H
FBOUT
H
L
H
L
Bypassed/Off
Bypassed/Off
on
on
PLL State
08-0298
2
PS8545D
11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
V
DDQ
, AV
DD
V
I
V
O
Tstg
Parame te r
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Output voltage range
Storage temperature
M in.
– 0 .5
– 0 .5
– 0 .5
– 65
V
DDQ
+0.5
M ax.
3. 6
V
Units
150
o
C
Note:
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Timing Requirements
(Over recommended operating free-air temperature)
AV
DD
, V
DDQ
= 2.5V ±0.2V
Symbol
De s cription
M in.
f
CK
t
DC
t
STAB
Operating clock frequency
(1,2)
Application clock
frequency
(3)
60
95
40
M ax.
17 0
170
60
100
MHz
%
μ
s
Units
Input clock duty cycle
PLL stabilization time after powerup
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is
not required to meet the other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
08-0298
3
PS8545D
11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
DC Specifications
Recommended Operating Conditions
Symbol
AV
DD
V
DDQ
V
OH
V
OL
V
IX
V
OX
V
IN
V
ID
V
OD
T
A
Analog/core supply voltage
Output supply voltage
High- level output voltage
Low- level output voltage
Input differential- pair crossing voltage
O utput differential- pair crossing voltage at the SDRAM clock input
Input voltage level
Input differential voltage between CLK and CLK
Output differential voltage between Y[n] and Y[n] and FBOUT
and FBOUT
O perating free air temperature
Parame te r
M in.
2.3
2.3
1. 8
0
(V
DDQ
/2) –0.2
(V
DDQ
/2) –0.2
–0.3
0 . 36
0.7
0
Nom.
2.5
2.5
M ax.
2.7
2.7
V
DDQ
0.5
(V
DDQ
/2) +0.2
(V
DDQ
/2) +0.2
V
DDQ
+0.3
V
DDQ
+0.6
V
DDQ
+0.6
70
°C
V
Units
Electrical Characteristics
Parame te r
V
IK
I
I
I
DDQ
I
ADD
C
I
All inputs
CLK, FBIN
Dynamic supply current of V
DDQ
Dynamic supply current of AV
DD
CLK and CLK
FBIN and FBIN
Te s t Conditions
I
I
= –18mA
V
I
= V
DDQ
or GND
V
DD
= 2.7V
(1)
V
DD
= 2.7V
(1)
V
I
= V
DD
or GND
2 . 5V
2. 0
A
VDD
, V
DDQ
2 . 3V
2 . 7V
M in.
Typ.
M a x.
–1.2
±10
300
12
3 .0
Units
V
μ
A
mA
mA
pF
Notes:
1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.
08-0298
4
PS8545D
11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
AC Specifications
Switching characteristics over recommended operating free-air temperature range, f
CLK
> 100 MHz (unless otherwise noted).
(See Figure 1 and 2)
AV
CC
, V
DDQ
= 2.5V ±0.2V
Parame te r
t(
θ)
tjit(cc)
tjit(per)
tjit(hper)
tsl(i)
tsl(o)
tsk(o)
De s cription
Static phase offset
(1)
Cycle- to- cycle jitter
Period jitter
Half- period jitter
Input clock slew rate
(2)
Output clock slew rate
(2)
Output clock skew
Diagram
M in.
Figure 4
Figure 3
Figure 6
Figure 7
Figure 8
Figure 8
Figure 5
–50
–75
–75
–100
1.0
1.0
Nom.
0
M ax
50
75
75
10 0
2 .0
2 .0
100
V/ns
ps
ps
Units
The PLL on the PI6CV855 meets all the above parameters while supporting SSC synthesizers with the following parameters
(3)
.
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
Phase angle
Notes:
1. Static Phase offset does not include jitter.
2. The slew rate is determined from the IBIS model with test load shown in Figure 1.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
3 0 .0
0 . 00
2
50.0
–0 . 5 0
kHz
%
MHz
–0.031
degrees
08-0298
5
PS8545D
11/12/08
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