– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3
hot
and
D3
cold
– Unused SerDes are disabled
◆
Testability and Debug Features
– Ability to read and write any internal register via the SMBus
◆
Eight General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in 27x27mm 420 ball BGA with 1mm ball spacing
◆
Bit
4
5
6
7
Slave
SMBus
Address
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment
Product Description
Utilizing standard PCI Express interconnect, the PES24N3A
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 24 integrated serial lanes. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification revision 1.1.
SMBus Interface
The PES24N3A contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES24N3A,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES24N3A to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
As shown in Figure 2, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES24N3A acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES24N3A registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES24N3A may be configured to operate in a split configuration as
shown in Figure 2(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES24N3A supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
Bit
1
2
3
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
Table 1 Master and Slave SMBus Address Assignment
2 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
PES24N3A
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES24N3A
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 2 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES24N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24N3A
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES24N3A generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES24N3A. In response to an I/O expander interrupt, the PES24N3A generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24N3A provides eight General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
The PES24N3A is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Trans-
action layers in compliance with PCI Express Base specification Revision 1.1. The PES24N3A can operate either as a store and forward or cut-
through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with
sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications.
Processor
North
Bridge
Memory
Memory
Memory
Memory
PES24N3A
PES24N3A
PES24N3A
PCI Express
Slots
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
Figure 3 I/O Expansion Application
3 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note:
In the PES24N3A, the two downstream ports are labeled port 2 and port 4.
Signal
PE0RP[7:0]
PE0RN[7:0]
PE0TP[7:0]
PE0TN[7:0]
PE2RP[7:0]
PE2RN[7:0]
PE2TP[7:0]
PE2TN[7:0]
PE4RP[7:0]
PE4RN[7:0]
PE4TP[7:0]
PE4TN[7:0]
PEREFCLKP[2:1]
PEREFCLKN[2:1]
Type
I
O
I
O
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 4.
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select.
This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
REFCLKM
I
Signal
MSMBADDR[4:1]
MSMBCLK
Type
I
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address.
These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
I/O
I
I/O
I/O
4 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Signal
GPIO[0]
Type
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
[size=4]What is a debugger? [/size] [size=4]A debugger is a debugging software that engineers or programmers can use to verify algorithms. The debugger can access the DSP hardware logic with the follo...
In the previous evaluation , we have set up the environment required for development, created a new project from scratch, and successfully printed Hello World
Next, I will give a score for the microco...
I just started headhunting and don't know where to post to find people. Please give me some advice. In addition, that classmate is a middleware developer. If he wants to change jobs, please contact me...
With the promotion and popularity of digital TV and VOD, this hardware-based subtitle overlay may soon become obsolete, but it may still have certain applications in some occasions, such as some simpl...
Does anyone know the interrupt response process of LM3S8962 under ucos2 (before entering the interrupt service routine) and the corresponding code? I have been looking at it for a long time but I can'...
1. Equipment Overview
Shell-and-tube heat exchangers are a common heat exchange device used in chemical evaporation and heating equipment. Currently, the tubesheets of shell-and-tube heat exch...[Details]
Capable of providing precise and efficient thermal management for artificial intelligence computing power, intelligent sensing and autonomous driving systems
Shenzhen, ...[Details]
1. Introduction
Electronic scales are gradually replacing traditional measuring tools like springs and balances in everyday life, such as electronic price computing scales and electronic weigh...[Details]
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[Details]
On August 20th, Tiantai Robotics Co., Ltd., along with strategic partners including Shandong Future Robotics Technology Co., Ltd., Shandong Future Data Technology Co., Ltd., and Gangzai Robotics Gr...[Details]
Since its invention in the mid-1940s, the microwave oven has evolved from a humble beginning to commercial use, entering homes in the 1960s and rapidly gaining popularity. Its basic functionality a...[Details]
Electric vehicles' 12V batteries don't rely on a generator to power them. Only gasoline-powered vehicles rely on the engine to drive a generator to generate electricity while driving, which is used...[Details]
Learned the following information.
Customer product: industrial computer motherboard
Glue application area: CPU/BGA filling
Glue color requirements: black or t...[Details]
According to Nikkei, Japan has performed poorly in responding to China's power semiconductor challenges.
There are five major companies in Japan's power chip market: Mitsubishi Electric,...[Details]
"We have successfully launched the first version of our dedicated chip for EMB brake-by-wire. Second-generation samples have also been successfully completed, and we are actively planning a third-g...[Details]
Lightweighting of automobiles is still a relatively unfamiliar term for automobiles. With the continuous improvement of environmental protection requirements, relevant regulations have also put for...[Details]
With growing environmental awareness, the continuous improvement of three-electric technology and the increasing deployment of infrastructure such as charging stations, the electrification of new e...[Details]
Charging is an essential topic for electric vehicles. Batteries are a core component of new energy vehicles. So, what's the optimal charge level for electric vehicles? Based on current battery tech...[Details]
Facial recognition, a biometric technology that uses facial features to authenticate identity, has rapidly become a global market hotspot in recent years as the technology has entered practical use...[Details]
introduction
With the development and widespread use of integrated circuits in power electronics design, electronic products are trending towards smaller sizes, more components, and greater fu...[Details]
Creative Market
京公网安备 11010802033920号
EEWORLD
