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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
REVISION HISTORY
Date
12/04/03
12/11/03
01/22/04
02/02/04
03/15/04
09/13/04
Revision Number
1.00
1.01
1.02
1.03
1.04
1.05
Description
First Release of Data Sheet
Minor text corrections made.
Addition of Features section as well as a couple of tables.
Text corrections.
Corrected Device ID Register bits 11:0 descriptions.
Corrected pin designation for P_RST to E22 in section 3.2.1
Corrected Cin max in section 10.2 (DC specifications) from 0.8pF to
8pF
Added power consumption data in Section 10.4
Corrected pin description for TEST_CE0 (Y23) in section 3.2.8
Correct package outline drawing in section 11
Added Pb-free & Green ordering information in section 12
Corrected Pb-free & Green ordering information from PI7C21P100NH
to PI7C21P100NHE in section 12
04/13/05
06/10/05
07/05/05
1.051
1.06
1.07
Page 3 of 77
July 5, 2005 Revision 1.07
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
TABLE OF CONTENTS
1
2
3
DESCRIPTION................................................................................................................................... 9
FEATURES ......................................................................................................................................... 9
SIGNAL DEFINITIONS.................................................................................................................. 10
3.1
SIGNAL TYPES ....................................................................................................................... 10
3.2
SIGNALS .................................................................................................................................. 10
3.2.1
PRIMARY BUS INTERFACE SIGNALS............................................................................... 10
3.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.......................................... 12
3.2.3
SECONDARY BUS INTERFACE SIGNALS......................................................................... 13
3.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.................................... 14
3.2.5
CLOCK SIGNALS................................................................................................................. 15
3.2.6
STRAPPING PINS AND MISCELLANEOUS SIGNALS ...................................................... 16
3.2.7
JTAG BOUNDARY SCAN AND TEST SIGNALS ................................................................. 17
3.2.8
TEST SIGNALS..................................................................................................................... 18
3.2.9
POWER AND GROUND SIGNALS...................................................................................... 18
3.3
PIN LIST ................................................................................................................................... 19
4
PCI BUS OPERATION.................................................................................................................... 22
4.1
TYPES OF TRANSACTIONS ................................................................................................. 22
4.2
WRITE TRANSACTIONS ....................................................................................................... 23
4.2.1
MEMORY WRITE TRANSACTIONS .................................................................................... 23
4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
PCI-X TO PCI-X ....................................................................................................................... 24
PCI TO PCI................................................................................................................................ 24
PCI TO PCI-X............................................................................................................................ 24
PCI-X TO PCI............................................................................................................................ 25
4.2.2
DELAYED/SPLIT WRITE TRANSACTIONS........................................................................ 25
4.2.3
IMMEDIATE WRITE TRANSACTIONS ............................................................................... 25
4.3
READ TRANSACTIONS......................................................................................................... 25
4.3.1
MEMORY READ TRANSACTIONS...................................................................................... 26
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
PCI-X TO PCI-X ....................................................................................................................... 26
PCI TO PCI................................................................................................................................ 26
PCI TO PCI-X............................................................................................................................ 26
PCI-X TO PCI............................................................................................................................ 27
4.3.2
4.3.3
4.3.4
4.3.5
I/O READ.............................................................................................................................. 27
CONFIGURATION READ ................................................................................................... 27
TYPE 1 CONFIGURATION READ ......................................................................................... 27
TYPE 0 CONFIGURATION READ ......................................................................................... 27
4.3.3.1
4.3.3.2
NON-PREFETCHABLE AND DWORD READS.................................................................. 28
PREFETCHABLE READS.................................................................................................... 28
PCI-X TO PCI-X AND PCI-X TO PCI .................................................................................... 28
PCI TO PCI................................................................................................................................ 28
PCI TO PCI-X............................................................................................................................ 29
4.3.5.1
4.3.5.2
4.3.5.3
4.3.6
DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY) ........................................ 29
4.4
CONFIGURATION TRANSACTIONS ................................................................................... 29
4.4.1
TYPE 0 ACCESS TO PI7C21P100....................................................................................... 30
4.4.2
TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 30
4.4.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 31
4.4.4
SPECIAL CYCLES ............................................................................................................... 32
5
TRANSACTION ORDERING ........................................................................................................ 32
5.1
5.2
6
GENERAL ORDERING GUIDELINES .................................................................................. 33
ORDERING RULES................................................................................................................. 33
CLOCKS............................................................................................................................................ 34
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July 5, 2005 Revision 1.07
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