PALCE22V10H-25PI/4 datasheet, PDF

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PALCE22V10H-25PI/4: DescriptionEE PLD, 25 ns, PDIP24; CategoryProgrammable logic devices Programmable logic; File Size336KB，34 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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PALCE22V10H-25PI/4 Overview

EE PLD, 25 ns, PDIP24

PALCE22V10H-25PI/4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	DIP
package instruction	0.300 INCH, SKINNY, PLASTIC, DIP-24
Contacts	24
Reach Compliance Code	_compli
ECCN code	EAR99
Other features	10 MACROCELLS, 1 EXTERNAL CLOCK, SHARED INPUT/CLOCK, VARIABLE PRODUCT TERMS
Architecture	PAL-TYPE
maximum clock frequency	33.3 MHz
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	30.734 mm
Dedicated input times	11
Number of I/O lines	10
Number of entries	22
Output times	10
Number of product terms	132
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	11 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-1

PALCE22V10Z COM'L: -25

IND: -15

PALCE22V10 and PALCE22V10Z

Families

DISTINCTIVE CHARACTERISTICS

24-Pin EE CMOS (Zero Power) Versatile PAL

As fast as 5-ns propagation delay and 142.8 MHz f

MAX

(external)

Low-power EE CMOS

10 macrocells programmable as registered or combinatorial, and active high or active

match application needs

Varied product term distribution allows up to 16 product terms per output for compl

functions

Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)

Global asynchronous reset and synchronous preset for initialization

Power-up reset for initialization and register preload for testability

Extensive third-party software and programmer support

24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC

5-ns and 7.5-ns versions utilize split leadframes for improved performance

GENERAL DESCRIPTION

The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI

ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z is an advanced PAL

device built with zero-power, high-speed, elec

erasable CMOS technology. It provides user-programmable logic for replacing conventi

power CMOS SSI/MSI gates and ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum st

current, the PALCE22V10Z allows battery-powered operation for an extended period.

The PAL device implements the familiar Boolean logic transfer function, the sum of prod

PAL device is a programmable AND array driving a ﬁxed OR array. The AND array is pro

to create custom product terms, while the OR array sums selected terms at the outputs.

The product terms are connected to the ﬁxed OR array with a varied distribution from 8 to

the outputs (see Block Diagram). The OR sum of the products feeds the output macroc

macrocell can be programmed as registered or combinatorial, and active-high or active

output conﬁguration is determined by two bits controlling two multiplexers in each ma

Publication#

16564

Amendment/

Rev:

Issue Date:

November 1998

Note that preset and reset control the ﬂip-ﬂop, not the output pin. The output level is de

by the output polarity selected.

Power-Up Reset

All ﬂip-ﬂops power up to a logic LOW for predictable system initialization. Outputs of t

PALCE22V10 will depend on the programmed output polarity. The V

rise must be mo

and the reset delay time is 1000ns maximum.

The register on the PALCE22V10 can be preloaded from the output pins to facilitate fun

testing of complex state machine designs. This feature allows direct loading of arbitrary

making it unnecessary to cycle through long test vector sequences to reach a desired st

addition, transitions from illegal states can be veriﬁed by loading illegal states and obse

proper recovery.

Security Bit

After programming and veriﬁcation, a PALCE22V10 design can be secured by programm

security EE bit. Once programmed, this bit defeats readback of the internal programme

by a device programmer, securing proprietary designs from competitors. When the secu

programmed, the array will read as if every bit is erased, and preload will be disabled.

The bit can only be erased in conjunction with erasure of the entire pattern.

Programming and Erasing

The PALCE22V10 can be programmed on standard logic programmers. It also may be e

reset a previously conﬁgured device back to its unprogrammed state. Erasure is automa

performed by the programming hardware. No special erase operation is required.

Quality and Testability

The PALCE22V10 offers a very high level of built-in quality. The erasability of the device

a direct means of verifying performance of all AC and DC parameters. In addition, this

complete programmability and functionality of the device to provide the highest progra

yields and post-programming functional yields in the industry.

Technology

The high-speed PALCE22V10 is fabricated with Vantis’ advanced electrically erasable (E

process. The array connections are formed with proven EE cells. Inputs and outputs are

to be compatible with TTL devices. This technology provides strong input clamp diode

slew-rate control, and a grounded substrate for clean switching.

PCI Compliance

The PALCE22V10H devices in the -5/-7/-10 speed grades are fully compliant with the

Bus Speciﬁcation

published by the PCI Special Interest Group. The PALCE22V10H’s pre

timing ensures compliance with the PCI AC speciﬁcations independent of the design.

Zero-Standby Power Mode

The PALCE22V10Z features a zero-standby power mode. When none of the inputs swit

extended period (typically 50 ns), the PALCE22V10Z will go into standby mode, shuttin

PALCE22V10 and PALCE22V10Z Families

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