V
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PI6C2502
Phase-Locked Loop Clock Driver
Product Description
The PI6C2502 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Product Features
•
High-Performance Phase-Locked-Loop Clock Distribution
for Networking,
•
Synchronous DRAM modules for server/workstation/
PC applications
•
Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
•
Zero Input-to-Output delay
•
Low jitter: Cycle-to-Cycle jitter ±100ps max.
•
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
•
Operates at 3.3V V
CC
•
Wide range of Clock Frequencies up to 80 MHz
•
Package (Pb-Free & Green): Plastic 8-pin SOIC Package (W)
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
CLK_IN
PLL
FB_IN
AV
CC
CLK_OUT
AGND
FB_OUT
CLK_OUT
1
2
3
4
8
CLK_IN
AV
CC
GND
FB_IN
8-Pin
W
7
6
5
FB_OUT
V
CC
Feedback
Zero Delay
Buffer
PI6C2502
Reference
Clock
Signal
CLK_OUT
18 Output
Non-Zero
Delay
Buffer
17
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
08-0298
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PI6C2502
Phase-Locked Loop Clock Driver
Pin Functions
Pin Name
CLK_IN
FB_IN
FB_OUT
Pin Numbe r
8
5
2
Type
I
I
O
De s cription
Reference Clock input. CLK_IN allows spread spectrum clock input.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Feedback output FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series- damping resistor of the same value
as the clock outputs CLK_OUT.
Clock outputs. These outputs provide low- skew copies of CLK_IN.
Each output has an embedded series- damping resistor.
Analog power supply. AV
C C
can be also used to bypass the PLL for
test purposes. When AV
C C
is strapped to ground, PLL is bypassed
and CLK_IN is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply.
Ground.
CLK_OUT
3
O
AV
C C
AGND
V
C C
GND
7
1
4
6
Power
Ground
Power
Ground
DC Specifications
(Absolute maximum ratings over operating free-air temperature range)
Symbol
V
I
V
O
I
O_DC
Power
T
STG
Parame te r
Input voltage range
–0 . 5
Output voltage range
DC output current
Maximum power dissipation at T
A
= 55
o
C in still air
Storage temperature
–6 5
100
1. 0
150
mA
W
o
C
M in.
M a x.
V
CC
+0.5
Units
V
Note:
Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Parame te r
I
CC
C
I
C
O
Te s t Conditions
V
I
= V
CC
or GND; I
O
= 0
(1)
V
I
= V
CC
or GND
V
CC
3.6V
M in.
Typ.
M ax.
10
Units
μA
pF
4
3.3V
6
V
O
=V
CC
or GND
Note:
1. Continuous Output Current
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PI6C2502
Phase-Locked Loop Clock Driver
Recommended Operating Conditions
Symbol
V
C C
V
IH
V
IL
V
I
T
A
Supply voltage
High level input voltage
Low level input voltage
Input voltage
Operating free- air temperature
0
0
Parame te r
M in.
3 .0
2.0
V
0.8
V
C C
70
ºC
M ax.
3.6
Units
Electrical Characteristics
(Over recommended operating free-air temperature range Pull Up/Down Currents, V
CC
= 3.0V)
Symbol
I
O H
Parame te r
Pull- up current
Condition
V
O U T
= 2.4V
V
O U T
= 2.0V
M in.
M a x.
−
18
−
30
Units
mA
I
O L
Pull- down current
V
O U T
= 0.8V
V
O U T
= 0.55V
25
17
AC Specifications Timing Requirements
(Over recommended ranges of supply voltage and operating free-air temperature)
Symbol
F
CLK
D
CYI
Clock frequency
Parame te r
M in.
25
40
M a x.
80
60
1
Units
MHz
%
ms
Input clock duty cycle
Stabilization Time after power up
Switching Characteristics
(Over recommended ranges of supply voltage and operating free-air temperature, C
L
=30pF)
Parame te r
tphase error without jitter
Jitter, cycle- to- cycle
Skew at 100 MHz
and 66 MHz
Duty cycle
tr, rise- time, 0.4V to 2.0V
tf, fall- time, 2.0V to 0.4V
From (Input)
CLK_IN
↑
at 100MHz and 66MHz
At 100 MHz and 66 MHz
CLK_OUT or FB_OUT
To (Output)
FB_IN
↑
CLK_OUT
CLK_OUT
or FB_OUT
V
C C
= 3.3V ±0.3V, 0-70°C
M in.
–150
–100
Typ.
M a x.
+150
Units
ps
+100
200
45
CLK_OUT
or FB_OUT
1.0
ns
1.1
55
%
Note:
These switching parameters are guaranteed by design.
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Ordering Information
Orde ring Code
PI6C2502WE
Package Name
W8
Package Type
8- pin 150- mil SOIC, Pb- Free & Green
Ope rating Range
Commercial
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PI6C2502
Phase-Locked Loop Clock Driver
Package Mechanical Information
Plastic 8-pin SOIC Package
DOCUMENT CONTROL NO.
8
PD - 1001
REVISION: F
.149
.157
DATE: 03/09/05
3.78
3.99
.0099
.0196
0.25
0.50
1
.189
.196
4.80
5.00
.0075
.0098
0.19
0.25
0.40
.016
1.27
.050
.016
.026
0.406
0.660
.053
.068
1.35
1.75
SEATING PLANE
.2284
.2440
5.80
6.20
1
REF
.050
BSC
1.27
.013
0.330
.020
0.508
.0040
0.10
.0098
0.25
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Notes:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012D/AA
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
DESCRIPTION: 8-Pin, 150-Mil Wide, SOIC
PACKAGE CODE: W
Notes:
1. Thermal characteristics can be found on the company website at www.pericom.com/packaging/
2. X = Tape & Reel
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
08-0298
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PS8382C
11/06/08
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