IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 35
2013 Integrated Device Technology, Inc
December 17, 2013
IDT 89HPES24NT24G2 Datasheet
Clocking
–
Supports 100 MHz and 125 MHz reference clock frequencies
–
Flexible port clocking modes
•
Common clock
•
Non-common clock
•
Local port clock with SSC (spread spectrum setting) and port
reference clock input
Hot-Plug and Hot Swap
–
Hot-plug controller on all ports
•
Hot-plug supported on all downstream switch ports
–
All ports support hot-plug using low-cost external I
2
C I/O
expanders
–
Configurable presence-detect supports card and cable appli-
cations
–
GPE output pin for hot-plug event notification
•
Enables SCI/SMI generation for legacy operating system
support
–
Hot-swap capable I/O
Power Management
–
Supports D0, D3hot and D3 power management states
–
Active State Power Management (ASPM)
•
Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
•
Configurable L0s and L1 entry timers allow performance/
power-savings tuning
–
SerDes power savings
•
Supports low swing / half-swing SerDes operation
•
SerDes associated with unused ports are turned off
•
SerDes associated with unused lanes are placed in a low
power state
Reliability, Availability, and Serviceability (RAS)
–
ECRC support
–
AER on all ports
–
SECDED ECC protection on all internal RAMs
–
End-to-end data path parity protection
–
Checksum Serial EEPROM content protected
–
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Initialization / Configuration
–
Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
–
Common switch configurations are supported with pin strap-
ping (no external components)
–
Supports in-system Serial EEPROM initialization/program-
ming
On-Die Temperature Sensor
–
Range of 0 to 127.5 degrees Celsius
–
Three programmable temperature thresholds with over and
under temperature threshold alarms
–
Automatic recording of maximum high or minimum low
temperature
9 General Purpose I/O
Test and Debug
–
Ability to inject AER errors simplifies in system error handling
software validation
–
On-chip link activity and status outputs available for several
ports
–
Per port link activity and status outputs available using
external I
2
C I/O expander for all remaining ports
–
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Standards and Compatibility
–
PCI Express Base Specification 2.1 compliant
–
Implements the following optional PCI Express features
•
Advanced Error Reporting (AER) on all ports
•
End-to-End CRC (ECRC)
•
Access Control Services (ACS)
•
Device Serial Number Enhanced Capability
•
Sub-System ID and Sub-System Vendor ID Capability
•
Internal Error Reporting
•
Multicast
•
VGA and ISA enable
•
L0s and L1 ASPM
•
ARI
Power Supplies
–
Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
Packaged in a 19mm x 19mm 324-ball Flip Chip BGA with
1mm ball spacing
Product Description
With Non-Transparent Bridging functionality and innovative Switch
Partitioning feature, the PES24NT24G2 allows true multi-host or multi-
processor communications in a single device. Integrated DMA control-
lers enable high-performance system design by off-loading data transfer
operations across memories from the processors. Each lane is capable
of 5 GT/s link speed in both directions and is fully compliant with PCI
Express Base Specification 2.1.
A non-transparent bridge (NTB) is required when two PCI Express
domains need to communicate to each other. The main function of the
NTB block is to initialize and translate addresses and device IDs to
allow data exchange across PCI Express domains. The major function-
alities of the NTB block are summarized in
Table 1.
2 of 35
December 17, 2013
IDT 89HPES24NT24G2 Datasheet
Block Diagram
24-Port Switch Core / 24 Gen2 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
SerDes
x1
x1
(Port 0)
(Ports 0 through 7 are not capable of merging with an adjacent port)
Figure 1 PES24NT24G2 Block Diagram
Port 23
Function
NTB ports
Mapping table
entries
Mapping windows
Number
Up to 8
Up to 64 for entire
device
Six 32-bits or three
64-bits
Description
Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Each device can have up to 64 masters ID for address and ID translations.
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets
a corresponding bit at the inbound doorbell in the other domain.
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Table 1 Non-Transparent Bridge Function Summary
Address translation Direct-address and
lookup table trans-
lations
Doorbell registers
Message registers
32 bits
4 inbound and out-
bound registers of
32-bits
3 of 35
December 17, 2013
IDT 89HPES24NT24G2 Datasheet
SMBus Interface
The PES24NT24G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES24NT24G2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES24NT24G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface
is also used by an external Hot-Plug I/O expander.
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
SSMBADDR2 pins. As shown in
Figure 2,
the master and slave SMBuses may only be used in a split configuration. In the split configuration, the
master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not
support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM
and I/O expander slaves.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 2 Split SMBus Interface Configuration
Hot-Plug Interface
The PES24NT24G2 supports PCI Express Hot-Plug on each downstream port (ports 1 through 23). To reduce the number of pins required on the
device, the PES24NT24G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface.
Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES24NT24G2 generates an SMBus transaction
to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is
received on the IOEXPINTN input pin (alternate function of GPIO) of the PES24NT24G2. In response to an I/O expander interrupt, the PES24NT24G2
generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24NT24G2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES24NT24G2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Note:
Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.
[table=98%] [tr][td] My graduation project involves the connection between the SP12 pressure sensor and the STC89C52 modules. Now I need to process the data collected by the SP12 through the single-ch...
: [b][font=宋体][size=16pt]Realization of Embedded Network System Based on[/size][/font][/b][b][font=宋体][size=16pt]S3C44B0X[/size][/font][/b][b][font=宋体][size=16pt] and[/size][/font][/b][b][font=Arial][...
[Abstract] With the development of wireless personal communication systems, new systems emerge in an endless stream, making it difficult for the wireless communication system based on hardware to adap...
Designing for automotive LCD displays larger than 5" can be complex. The display source driver requires a supply rail called analog voltage device drain (AVDD) in the 10V to 15V range and two supply ...[Details]
On April 17, the U.S. Department of Commerce suddenly announced that it would completely ban U.S. companies from
selling parts, goods, software and technology
to
ZTE
within 7 years. This als...[Details]
ZTE,
caught
in the vortex of
the US ban on the sale
of chips
, has sounded the alarm for China's information technology industry and revealed China's "chip disease". Let's follow the ...[Details]
In order to strengthen the management of new energy vehicle charging facilities in our city, prevent and reduce accidents, protect the lives and property of the people, and improve the public safet...[Details]
1.MAX31865 (1 Introduction The MAX31865 is an easy-to-use thermistor-to-digital converter optimized for platinum resistance temperature detectors (RTDs). External resistors set the RTD sensitivity, a...[Details]
Friends who work in the photovoltaic industry, do you still remember the hard work on June 30 last year? How many people worked late into the night for months in a row just to connect to the grid a...[Details]
After we understand the use of libopencm3, we find that libopencm3 is only suitable for small projects. Its biggest feature is the convenience of USB. So when we configure large projects, is there a ...[Details]
Development Background: 1. Main chip - STM32F207VCT6; 2. TCP/IP protocol stack - LWIP, transplanted based on ST routines; 3. Operating system - none (bare metal); Anomalies: 1. Power on the device wi...[Details]
The last two blogs talked about a version problem of STM32CubeMX and the problem of hardware reset. When you solve these two problems, you will find that after the program is burned into the board, t...[Details]
Automotive LCD Instrument Clock EMI Solution As early as 2014, the market size of China's automotive full LCD instrument has reached 3.506 billion yuan, and it is expected that by 2020, this s...[Details]
In the Chinese automobile market, the trend of new energy vehicles and driverless cars is leading the transformation of China's automobile industry. As the world's largest automobile market, "Chinese...[Details]
With the implementation of the first version of the NR sub-6GHz draft of 3GPP in December 2017, and the subsequent Phase 2 drafts, semiconductor manufacturers and terminal manufacturers began to ...[Details]
Temperature, humidity and irradiance are must-measure items in the photovoltaic industry. However, most of the current data collection is done by storing data in USB flash drives for offline analys...[Details]
1. Introduction to MC68K CPU The MC683xx series of microcontrollers are composed of the famous MOTOROLA 32-bit microprocessors such as MC68K, 68020, 68040, and the compatible 68K, CPU32, CPU3...[Details]
Analog electronics
京公网安备 11010802033920号
EEWORLD
