MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
5 V PCM Codec-Filter
The MC14LC5480 is a general purpose per channel PCM Codec–Filter with
pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP,
SOG, and SSOP packages. This device performs the voice digitization and
reconstruction as well as the band limiting and smoothing required for PCM
systems. This device is designed to operate in both synchronous and
asynchronous applications and contains an on–chip precision reference
voltage.
This device has an input operational amplifier whose output is the input to the
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
active R–C filter, the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band–
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
The MC14LC5480 PCM Codec–Filter accepts a variety of clock formats,
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
environments. This device also maintains compatibility with Motorola’s family of
Telecommunication products, including the MC14LC5472 U–Interface Trans-
ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-
coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120
SLIC.
The MC14LC5480 PCM Codec–Filter utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
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Pin for Pin Replacement for the MC145480
Single 5 V Power Supply
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
Fully–Differential Analog Circuit Design for Lowest Noise
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law and A–Law Companding by Pin Selection
On–Chip Precision Reference Voltage (1.575 V)
Push–Pull 300
Ω
Power Drivers with External Gain Adjust
MC145536EVK is the Evaluation Kit that Also Includes the MC145532
ADPCM Transcoder
MC14LC5480
P SUFFIX
PLASTIC DIP
CASE 738
20
1
20
1
DW SUFFIX
SOG PACKAGE
CASE 751D
Freescale Semiconductor, Inc...
20
1
SD SUFFIX
SSOP
CASE 940C
ORDERING INFORMATION
MC14LC5480P
MC14LC5480DW
MC14LC5480SD
Plastic DIP
SOG Package
SSOP
PIN ASSIGNMENT
RO+
RO-
PI
PO-
PO+
VDD
FSR
DR
BCLKR
PDI
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VAG
TI+
TI-
TG
Mu/A
VSS
FST
DT
BCLKT
MCLK
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 0.1
5/96
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RO +
RO -
FREQ
PI
FSR
PO -
-
+
BCLKR
Mu/A
SEQUENCE
AND
CONTROL
1.575 V
REF
1
2.4 V
REFERENCE
PDI
MCLK
BCLKT
FST
DAC
RECEIVE
SHIFT
REGISTER
DR
SHARED
DAC
PO +
-1
VDD
VSS
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VAG
TG
TI -
TI +
-
+
FREQ
ADC
TRANSMIT
SHIFT
REGISTER
DT
Figure 1. MC14LC5480 PCM Codec–Filter Block Diagram
DEVICE DESCRIPTION
A PCM Codec–Filter is used for digitizing and reconstruct-
ing the human voice. These devices are used primarily for
the telephone network to facilitate voice switching and trans-
mission. Once the voice is digitized, it may be switched by
digital switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from ‘‘COder’’ for the analog–to–digital
converter (ADC) used to digitize voice, and ‘‘DECoder’’ for
the digital–to–analog converter (DAC) used for reconstruct-
ing voice. A codec is a single device that does both the ADC
and DAC conversions.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This may be accomplished with a linear 13–bit ADC and
DAC, but will far exceed the required signal–to–distortion
ratio at larger amplitudes than 40 dB below the peak ampli-
tude. This excess performance is at the expense of data per
sample. Two methods of data reduction are implemented by
compressing the 13–bit linear scheme to companded
pseudo–logarithmic 8–bit schemes. The two companding
schemes are: Mu–255 Law, primarily in North America and
Japan; and A–Law, primarily used in Europe. These com-
panding schemes are accepted world wide. These compand-
ing schemes follow a segmented or ‘‘piecewise–linear’’ curve
formatted as sign bit, three chord bits, and four step bits. For
a given chord, all sixteen of the steps have the same voltage
weighting. As the voltage of the analog input increases, the
four step bits increment and carry to the three chord bits
which increment. When the chord bits increment, the step
bits double their voltage weighting. This results in an effec-
tive resolution of six bits (sign + chord + four step bits) across
a 42 dB dynamic range (seven chords above 0, by 6 dB per
chord).
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the in–band signal. The telephone line is also subject to
50/60 Hz power line coupling, which must be attenuated
from the signal by a high–pass filter before the analog–to–
digital converter.
The digital–to–analog conversion process reconstructs a
staircase version of the desired in–band signal, which has
spectral images of the in–band signal modulated about the
sample frequency and its harmonics. These spectral images
are called aliasing components, which need to be attenuated
to obtain the desired signal. The low–pass filter used to at-
tenuate these aliasing components is typically called a re-
construction or smoothing filter.
The MC14LC5480 PCM Codec–Filter has the codec, both
presampling and reconstruction filters, a precision voltage
reference on–chip, and requires no external components.
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PIN DESCRIPTIONS
POWER SUPPLY
VDD
Positive Power Supply (Pin 6)
This is the most positive power supply and is typically con-
nected to + 5 V. This pin should be decoupled to VSS with a
0.1
µF
ceramic capacitor.
VSS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
VAG
Analog Ground Output (Pin 20)
This output pin provides a mid–supply analog ground reg-
ulated to 2.4 V. This pin should be decoupled to VSS with a
0.01
µF
to 0.1
µF
ceramic capacitor. All analog signal pro-
cessing within this device is referenced to this pin. If the au-
dio signals to be processed are referenced to V SS, then
special precautions must be utilized to avoid noise between
V SS and the VAG pin. Refer to the applications information in
this document for more information. The VAG pin becomes
high impedance when this device is in the powered down
mode.
CONTROL
Mu/A
Mu/A Law Select (Pin 16)
This pin controls the compression for the encoder and the
expansion for the decoder. Mu–Law companding is selected
when this pin is connected to VDD and A–Law companding is
selected when this pin is connected to VSS.
PDI
Power–Down Input (Pin 10)
This pin puts the device into a low power dissipation mode
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO+, RO–, PO–, PO+, TG, VAG, and DT to
become high impedance. The device will operate normally
when a logic 1 is applied to this pin. The device goes through
a power–up sequence when this pin is taken to a logic 1
state, which prevents the DT PCM output from going low im-
pedance for at least two FST cycles. The filters must settle
out before the DT PCM output or the RO+ or RO– receive
analog outputs will represent a valid analog signal.
ANALOG INTERFACE
TI+
Transmit Analog Input (Non–Inverting) (Pin 19)
This is the non–inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the V SS
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.2 V, to V DD minus 2 V. This is an FET
gate input. Connecting the TI+ pin to V DD will place this am-
plifier’s output (TG) into a high–impedance state, thus allow-
ing the TG pin to serve as a high–impedance input to the
transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
This is the inverting input of the transmit gain setting op-
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to VDD – 2 V. This is an FET gate input.
Connecting the TI+ pin to VDD will place this amplifier’s out-
put (TG) into a high–impedance state, thus allowing the TG
pin to serve as a high–impedance input to the transmit filter.
TG
Transmit Gain (Pin 17)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kΩ load. Connecting the TI+
pin to VDD will place this amplifier’s output (TG) into a high–
impedance state, thus allowing the TG pin to serve as a
high–impedance input to the transmit filter. All signals at this
pin are referenced to the VAG pin. This pin is high impedance
when the device is in the powered down mode.
RO+
Receive Analog Output (Non–Inverting) (Pin 1)
This is the non–inverting output of the receive smoothing
filter from the digital–to–analog converter. This output is
capable of driving a 2 kΩ load to 1.575 V peak referenced to
the VAG pin. This pin is high impedance when the device is in
the powered down mode.
RO–
Receive Analog Output (Inverting) (Pin 2)
This is the inverting output of the receive smoothing filter
from the digital–to–analog converter. This output is capable
of driving a 2 kΩ load to 1.575 V peak referenced to the VAG
pin. This pin is high impedance when the device is in the
powered down mode.
PI
Power Amplifier Input (Pin 3)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier is internally tied to the
VAG pin. The PI and PO– pins are used with external resis-
tors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connect-
ing PI to VDD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
This is the inverting power amplifier output, which is used
to provide a feedback signal to the PI pin to set the gain of
the push–pull power amplifier outputs. This pin is capable of
driving a 300
Ω
load to PO+. The PO+ and PO– outputs are
differential (push–pull) and capable of driving a 300
Ω
load to
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage
and signal reference of this output is the VAG pin. The VAG
pin cannot source or sink as much current as this pin, and
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therefore low impedance loads must be between PO+ and
PO–. Connecting PI to VDD will power down the power driver
amplifiers and the PO+ and PO– outputs will be high imped-
ance. This pin is also high impedance when the device is
powered down by the PDI pin.
PO+
Power Amplifier Output (Non–Inverting) (Pin 5)
This is the non–inverting power amplifier output, which is
an inverted version of the signal at PO–. This pin is capable
of driving a 300
Ω
load to PO–. Connecting PI to VDD will
power down the power driver amplifiers and the PO+ and
PO– outputs will be high impedance. This pin is also high im-
pedance when the device is powered down by the PDI pin.
See PI and PO– for more information.
DIGITAL INTERFACE
FSR
Frame Sync, Receive (Pin 7)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock, which synchronizes
the input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes. When an ISDN mode (IDL or GCI) has
been selected with BCLKR, this pin selects either B1 (logic 0)
or B2 (logic 1) as the active data channel.
BCLKR
Bit Clock, Receive (Pin 9)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,
and DR become IDL Interface compatible. When this pin is
held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-
face compatible.
DR
Data, Receive (Pin 8)
This pin is the PCM data input, and when in a Long Frame
Sync or Short Frame Sync mode is controlled by FSR and
BCLKR. When in the IDL or GCI mode, this data transfer is
controlled by FST and BCLKT. FSR and BCLKR select the
B channel and ISDN mode, respectively.
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MCLK
Master Clock (Pin 11)
This is the master clock input pin. The clock signal applied
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
this pin to the clock at FST (8 kHz) and will automatically
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-
chronous and approximately rising edge aligned to FST. For
optimum performance at frequencies of 1.536 MHz and
higher, MCLK should be synchronous and approximately ris-
ing edge aligned to the rising edge of FST. In many ap-
plications, MCLK may be tied to the BCLKT pin.
FST
Frame Sync, Transmit (Pin 14)
This pin accepts an 8 kHz clock that synchronizes the out-
put of the serial PCM data at the DT pin. This input is com-
patible with various standards including IDL, Long Frame
Sync, Short Frame Sync, and GCI formats. If both FST and
FSR are held low for several 8 kHz frames, the device will
power down.
BCLKT
Bit Clock, Transmit (Pin 12)
This pin controls the transfer rate of transmit PCM data. In
the IDL and GCI modes it also controls the transfer rate of
the receive PCM data. This pin can accept any bit clock fre-
quency from 64 to 4096 kHz for Long Frame Sync and Short
Frame Sync timing. This pin can accept clock frequencies
from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz
to 6.176 MHz for GCI timing mode.
DT
Data, Transmit (Pin 13)
This pin is controlled by FST and BCLKT and is high im-
pedance except when outputting PCM data. When operating
in the IDL or GCI mode, data is output in either the B1 or B2
channel as selected by FSR. This pin is high impedance
when the device is in the powered down mode.
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of this device includes a low–noise,
three–terminal op amp capable of driving a 2 kΩ load. This
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its
output is TG (Pin 17). This op amp is intended to be confi-
gured in an inverting gain circuit. The analog signal may be
applied directly to the TG pin if this transmit op amp is inde-
pendently powered down by connecting the TI+ and TI–
inputs to the VDD power supply. The TG pin becomes high
impedance when the transmit op amp is powered down. The
TG pin is internally connected to a 3–pole anti–aliasing pre–
filter. This pre–filter incorporates a 2–pole Butterworth active
low–pass filter, followed by a single passive pole. This pre–
filter is followed by a single–ended to differential converter
that is clocked at 512 kHz. All subsequent analog processing
utilizes fully–differential circuitry. The next section is a fully–
differential, 5–pole switched–capacitor low–pass filter with a
3.4 kHz frequency cutoff. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff fre-
quency of about 200 Hz. This high–pass stage has a trans-
mission zero at dc that eliminates any dc coming from the
analog input or from accumulated op amp offsets in the pre-
ceding filter stages. The last stage of the high–pass filter is
an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and digital–to–
analog converter (DAC) are shared by the transmit and re-
ceive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are virtually independent of tempera-
ture and power supply voltage. A binary–weighted capacitor
array (CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed
comparator to implement a successive–approximation con-
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version algorithm. All of the analog circuitry involved in the
data conversion (the voltage reference, RDAC, CDAC, and
comparator) are implemented with a differential architecture.
The receive section includes the DAC described above, a
sample and hold amplifier, a 5–pole, 3400 Hz switched ca-
pacitor low–pass filter with sinX/X correction, and a 2–pole
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing fil-
ter is buffered by an amplifier, which is output at the RO+ and
RO– pins. These outputs are capable of driving a 4 kΩ load
differentially or a 2 kΩ load to the VAG pin. The MC14LC5480
also has a pair of power amplifiers that are connected in a
push–pull configuration. The PI pin is the inverting input to
the PO– power amplifier. The non–inverting input is internally
tied to the VAG pin. This allows this amplifier to be used in an
inverting gain circuit with two external resistors. The PO+
amplifier has a gain of minus one, and is internally con-
nected to the PO– output. This complete power amplifier cir-
cuit is a differential (push–pull) amplifier with adjustable gain
that is capable of driving a 300
Ω
load to +12 dBm. The
power amplifier may be powered down independently of the
rest of the chip by connecting the PI pin to VDD.
The DT output will remain in a high–impedance state for at
least two FST pulses after power–up.
MASTER CLOCK
Since this codec–filter design has a single DAC architec-
ture, the MCLK pin is used as the master clock for all analog
signal processing including analog–to–digital conversion,
digital–to–analog conversion, and for transmit and receive fil-
tering functions of this device. The clock frequency applied to
the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,
1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-
vice has a prescaler that automatically determines the proper
divide ratio to use for the MCLK input, which achieves the re-
quired 256 kHz internal sequencing clock. The clocking re-
quirements of the MCLK input are independent of the PCM
data transfer mode (i.e., Long Frame Sync, Short Frame
Sync, IDL mode, or GCI mode).
DIGITAL I/O
The MC14LC5480 is pin selectable for Mu–Law or A–Law.
Table 1 shows the 8–bit data word format for positive and
negative zero and full scale for both companding schemes
(see Tables 3 and 4 at the end of this document for a com-
plete PCM word conversion table). Table 2 shows the series
of eight PCM words for both Mu–Law and A–Law that corre-
spond to a digital milliwatt. The digital mW is the 1 kHz cal-
ibration signal reconstructed by the DAC that defines the
absolute gain or 0 dBm0 Transmission Level Point (TLP) of
the DAC. The 0 dBm0 level for Mu–Law is 3.17 dB below the
maximum level for an unclipped tone signal. The 0 dBm0
level for A–Law is 3.14 dB below the maximum level for an
unclipped tone signal. The timing for the PCM data transfer is
independent of the companding scheme selected. Refer to
Figure 2 for a summary and comparison of the four PCM
data interface modes of this device.
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POWER–DOWN
There are two methods of putting this device into a low
power consumption mode, which makes the device nonfunc-
tional and consumes virtually no power. PDI is the power–
down input pin which, when taken low, powers down the
device. Another way to power the device down is to hold both
the FST and FSR pins low. When the chip is powered down,
the VAG, TG, RO+, RO–, PO+, PO–, and DT outputs are high
impedance. To return the chip to the power–up state, PDI
must be high and the FST frame sync pulse must be present.
Table 1. PCM Codes for Zero and Full Scale
Mu–Law
Level
L
l
+ Full Scale
+ Zero
– Zero
– Full Scale
Sign Bit
1
1
0
0
Chord Bits
000
111
111
000
Step Bits
0000
1111
1111
0000
Sign Bit
1
1
0
0
A–Law
Chord Bits
010
101
101
010
Step Bits
1010
0101
0101
1010
Table 2. PCM Codes for Digital mW
Mu–Law
Phase
Ph
π/8
3π/8
5π/8
7π/8
9π/8
11π/8
13π/8
15π/8
Sign Bit
0
0
0
0
1
1
1
1
Chord Bits
001
000
000
001
001
000
000
001
Step Bits
1110
1011
1011
1110
1110
1011
1011
1110
Sign Bit
0
0
0
0
1
1
1
1
A–Law
Chord Bits
011
010
010
011
011
010
010
011
Step Bits
0100
0001
0001
0100
0100
0001
0001
0100
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