ICs for Communications
Multichannel Network Interface Controller for HDLC
MUNICH32
PEB 20320 Version 3.4
User’s Manual 01.2000
DS3
•
PEB 20320
Revision History:
Previous Version:
Page
(in previous
Version)
Page
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Version)
Current Version: 01.2000
User’s Manual 1998-06-01 DS2 (V3.4)
Subjects (major changes since last revision)
Package P-TQFP-176-1 removed from User’s Manual.
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Edition 01.2000
Published by Infineon Technologies AG,
SC,
Balanstraße 73,
81541 München
©
Infineon Technologies AG 2000.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
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Critical components
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with
the express written approval of the Infineon Technologies AG.
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expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
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PEB 20320
Preface
The Multichannel Network Interface Controller for HDLC (MUNICH32) is a Multichannel
Protocol Controller for a wide area of telecommunication and data communication
applications.
Organization of this Document
This User’s Manual is divided into 9 chapters. It is organized as follows:
• Chapter 1, Introduction
Gives a general description of the product and its family, lists the key features, and
presents some typical applications.
• Chapter 2, Functional Description
This chapter provides a detailed description of the interfaces and the protocol modes.
• Chapter 3, Operational Description
Provides a description of MUNICH32 reset procedure and initialization.
• Chapter 4, Detailed Register Description
Gives a detailed description of the shared memory organization.
• Chapter 5, Application Notes
• Chapter 6, Application Hints
• Chapter 7, Electrical Characteristics
Gives a detailed description of all electrical DC and AC characteristics and provides
timing diagrams and values for all interfaces.
• Chapter 8, Package Outlines
• Chapter 9, Appendix
This chapter provides source code examples.
Your Comments
We welcome your comments on this document as we are continuously aiming at
improving our documentation. Please send your remarks and suggestions by e-mail to
sc.docu_comments@infineon.com
Please provide in the subject of your e-mail:
device name (MUNICH32), device number (PEB 20320), device version (Version 3.4),
and in the body of your e-mail:
document type (User’s Manual), issue date (01.2000) and document revision number
(DS3).
User’s Manual
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01.2000
PEB 20320
User’s Manual
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PEB 20320
Table of Contents
1
1.1
1.2
1.3
1.4
1.5
1.6
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.4
2.5
3
3.1
3.2
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.4
5
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.1.3
5.1.1.4
5.1.2
5.1.3
5.1.3.1
Page
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
DMA Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Basic Functional Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Boundary Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Operational Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Detailed Register Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Organization of the Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Control and Configuration Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Action Specification (Read Once After Each Action Request Pulse) . . .136
Interrupt Queue Specification
. . . . . . . . . . . . . . . . . . . . . . .140
Interrupt Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Channel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Current Receive and Transmit Descriptor Address
. . . . . . . . . . . . . .161
Transmit Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Receive Descriptor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Application Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Test Loop Definitions for the MUNICH32 . . . . . . . . . . . . . . . . . . . . . . .173
Internal Complete Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Internal Channelwise Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
External Complete Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
External Channelwise Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Test Loop Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Test Loop Deactivation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . .176
Software Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
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