CY23FS08
Failsafe™ 2.5 V/3.3 V Zero Delay Buffer
Failsafe™ 2.5 V/3.3 V Zero Delay Buffer
Features
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Functional Description
The CY23FS08 is a FailSafe™ Zero Delay Buffer with two
reference clock inputs and eight phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
Continuous, glitch-free operation is achieved by using a DCXO,
which serves as a redundant clock source in the event of a
reference clock failure by maintaining the last frequency and
phase information of the reference clock.
The unique feature of the CY23FS08 is that the DCXO is in fact
the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically
resynchronizes to the external clock.
The frequency of the crystal connected to the DCXO, must be
chosen to be an integer factor of the frequency of the reference
clock. This factor is set by four select lines: S[4:1]. see
Configuration Table
on page 4. The CY23FS08 has three split
power supplies; one for core, another for Bank A outputs, and
the third for Bank B outputs. Each output power supply, except
VDDC can be connected to either 2.5 V or 3.3 V. VDDC is the
power supply pin for internal circuits and must be connected to
3.3 V.
Internal DCXO for continuous glitch-free operation
Zero input-output propagation delay
100 ps typical output cycle-to-cycle jitter
110 ps typical output-output skew
1 MHz to 200 MHz reference input
Supports industry standard input crystals
200 MHz (commercial), 166 MHz (industrial) outputs
5 V tolerant inputs
Phase-locked loop (PLL) bypass mode
Dual reference inputs
28-pin SSOP
Split 2.5 V or 3.3 V output power supplies
3.3 V core power supply
Industrial temperature available
Logic Block Diagram
XIN XOUT
REFSEL
DCXO
REF1
REF2
FBK
Failsafe
TM
Block
PLL
4
4
CLKA[1:4]
CLKB[1:4]
Decoder
FAIL# /SAFE
S[4:1]
4
Cypress Semiconductor Corporation
Document Number: 38-07518 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 10, 2014
CY23FS08
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Configuration Table .......................................................... 4
FailSafe Function .............................................................. 4
XTAL Selection Criteria and Application Example ...... 8
Absolute Maximum Conditions ..................................... 10
Recommended Pullable Crystal Specifications .......... 10
Operating Conditions ..................................................... 11
DC Electrical Characteristics ........................................ 11
Switching Characteristics .............................................. 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 38-07518 Rev. *H
Page 2 of 17
CY23FS08
Pinouts
Figure 1. 28-pin SSOP pinout
REF1
REF2
VSSB
CLKB1
CLKB2
S2
S3
VDDB
VSSB
CLKB3
CLKB4
VDDB
VDDC
XIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CY23FS08
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REFSEL
FBK
VSSA
CLKA1
CLKA2
S1
S4
VDDA
VSSA
CLKA3
CLKA4
VDDA
FAIL#/SAFE
XOUT
28-pin SSOP
Pin Definitions
Pin Number
1, 2
4, 5, 10, 11
25, 24, 19, 18
27
23, 6, 7, 22
14
15
16
13
8, 12
3, 9
17, 21
20, 26
28
Pin Name
REF1, REF2
Reference clock inputs.
[1]
5 V tolerant.
CLKB[1:4]
CLKA[1:4]
FBK
S[1:4]
XIN
XOUT
VDDC
VDDB
VSSB
VDDA
VSSA
REFSEL
Bank B clock outputs.
[2, 3]
Bank A clock outputs.
[2, 3]
Feedback input to the PLL.
[2]
Frequency select pins/PLL and DCXO bypass.
[4]
Reference crystal input.
Reference crystal output.
3.3 V power supply for the internal circuitry.
2.5 V or 3.3 V power supply for Bank B outputs.
Ground.
2.5 V or 3.3 V power supply for Bank A outputs.
Ground.
Reference select.
Selects the active reference clock from either REF1 or REF2.
When REFSEL = 1, REF1 is selected. When REFSEL = 0, REF2 is selected.
Description
FAIL#/SAFE
Valid reference indicator.
A high level indicates a valid reference input.
Notes
1. Weak pull downs on these inputs.
2. For normal operation, connect either one of the eight clock outputs to the FBK input.
3. Weak pull downs on all CLK outputs.
4. Weak pull ups on these inputs.
Document Number: 38-07518 Rev. *H
Page 3 of 17
CY23FS08
Configuration Table
S[4:1]
0000
1000
1110
0101
1011
0011
1001
1111
1100
0001
0110
1101
0100
1010
0010
0111
8.33
9.50
8.50
8.33
8.33
8.33
8.00
8.00
8.33
8.33
8.33
8.33
8.33
8.33
8.33
30
30
30
30
30
30
25
25
30
30
30
30
30
30
30
16.67
57.00
6.80
25.00
2.78
8.33
32.00
64.00
1.04
4.17
16.67
4.17
12.50
1.39
6.25
60.00
180.00
24.00
90.00
10.00
30.00
100.00
200.00
3.75
15.00
60.00
15.00
45.00
5.00
22.50
XTAL (MHz)
Min
Max
REF (MHz)
Min
Max
OUT (MHz)
Min
8.33
28.50
1.70
6.25
2.78
8.33
32.00
64.00
2.08
8.33
33.33
16.67
50.00
11.11
50.00
Max
30.00
90.00
6.00
22.50
10.00
30.00
100.00
200.00
7.50
30.00
120.00
60.00
180.00
40.00
180.00
REF:OUT
Ratio
2
2
4
4
×1
×1
×1
×1
×2
×2
×2
×4
×4
×8
×8
REF:XTAL Out:XTAL Ratio
Ratio
2
6
4/5
3
1/3
1
4
8
1/8
1/2
2
1/2
3/2
1/6
3/4
1
3
1/5
3/4
1/3
1
4
8
1/4
1
4
2
6
4/3
6
PLL and DCXO Bypass mode
FailSafe Function
The CY23FS08 is targeted at clock distribution applications that
requires or may require continued operation if the main reference
clock fails. Existing approaches to this requirement have used
multiple reference clocks with either internal or external methods
to switch between references. The problem with this technique
is that it leads to interruptions (or glitches) when transitioning
from one reference to another, often requiring complex external
circuitry or software to maintain system stability. The technique
implemented in this design completely eliminates any switching
of references to the PLL, greatly simplifying system design.
The CY23FS08 PLL is driven by the crystal oscillator, which is
phase-aligned to an external reference clock so that the output
of the device is effectively phase-aligned to reference via the
external feedback loop. This is accomplished by using a digitally
controlled capacitor array to pull the crystal frequency over an
approximate range of ±300 ppm from its nominal frequency.
In this mode, if the reference frequency fails (that is, stops or
disappears), the DCXO maintains its last setting and a flag signal
(FAIL#/SAFE) is set to indicate failure of the reference clock.
The CY23FS08 provides four select bits, S1 through S4 to
control the reference to crystal frequency ratio. The DCXO is
internally tuned to the phase and frequency of the external
reference only when the reference frequency divided by this ratio
is within the DCXO capture range. If the frequency is out of
range, a flag is set on the FAIL#/SAFE pin notifying the system
that the selected reference is not valid. If the reference moves in
range, then the flag is cleared, indicating to the system that the
selected reference is valid.
Figure 2. Fail#/Safe Timing for Input Reference Failing Catastrophically
REF
O UT
F A IL # /S A F E
t
F S L
t
F S H
Document Number: 38-07518 Rev. *H
Page 4 of 17
CY23FS08
Figure 3. Fail#/Safe Timing Formula
Table 1. Failsafe Timing Table
Parameter
t
FSL
t
FSH
Description
Fail#/Safe Assert Delay
Fail#/Safe Deassert Delay
Conditions
Measured at 80% to 20%, Load = 15 pF
Measured at 80% to 20%, Load = 15 pF
See
Figure 3
Min
Max
See
Figure 3
Unit
ns
ns
Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range
Reference + 300 ppm
Reference
Reference - 300 ppm
Reference Off
Frequency
Output + 300 ppm
Output
Output - 300 ppm
Fail#/Safe
Volt
t
FSH
t
FSL
Time
Document Number: 38-07518 Rev. *H
Page 5 of 17
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