POR Specifications....................................................................................................................................................81
AS Configuration Timing............................................................................................................................................86
DCLK Frequency Specification in the AS Configuration Scheme....................................................................................... 87
Minimum Configuration Time Estimation......................................................................................................................91
Remote System Upgrades......................................................................................................................................... 93
User Watchdog Internal Circuitry Timing Specifications..................................................................................................93
Document Revision History for the Intel Arria 10 Device Datasheet.......................................................................................... 99
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®
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Intel
®
Arria
®
10 Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing
for Intel
®
Arria
®
10 devices.
Intel Arria 10 devices are offered in extended and industrial grades. Extended devices are offered in –E1 (fastest), –E2, and –
E3 speed grades. Industrial grade devices are offered in the –I1, –I2, and –I3 speed grades.
The suffix after the speed grade denotes the power options offered in Intel Arria 10 devices.
•
•
•
•
L—enables the device to operate at low static power while maintaining excellent performance.
S—standard power specification.
V—enables the device to run at lower than default V
CC
, reducing static and dynamic power while retaining equivalent
performance.
H—small device with high performance at the fastest speed grade (–1).
Related Information
Intel Arria 10 Device Overview
Provides more information about the densities and packages of devices in the Intel Arria 10 family.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel Arria 10 devices.
Operating Conditions
Intel Arria 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Intel Arria 10 devices, you must consider the operating requirements described in this section.
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks
of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel
assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
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®
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®
10 Device Datasheet
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Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel Arria 10 devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
Caution:
Table 1.
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Absolute Maximum Ratings for Intel Arria 10 Devices
Symbol
V
CC
V
CCP
V
CCERAM
V
CCPT
V
CCBAT
V
CCPGM
V
CCIO
Core voltage power supply
Periphery circuitry and transceiver fabric interface power supply
Embedded memory power supply
Power supply for programmable power technology and I/O pre-driver
Battery back-up power supply for design security volatile key register
Configuration pins power supply
I/O buffers power supply
Description
Condition
—
—
—
—
—
(1)
Minimum
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
Maximum
1.21
1.21
1.36
2.46
2.46
2.46
4.10
2.46
2.46
1.34
1.34
2.46
1.27
4.10
2.46
2.46
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
continued...
3 V I/O
LVDS I/O
V
CCA_PLL
V
CCT_GXB
V
CCR_GXB
V
CCH_GXB
V
CCL_HPS
V
CCIO_HPS
Phase-locked loop (PLL) analog power supply
Transmitter power supply
Receiver power supply
Transceiver output buffer power supply
HPS core voltage and periphery circuitry power supply
HPS I/O buffers power supply
—
—
—
—
—
3 V I/O
LVDS I/O
V
CCIOREF_HPS
HPS I/O pre-driver power supply
—
(1)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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®
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Symbol
V
CCPLL_HPS
I
OUT
T
J
T
STG
HPS PLL power supply
DC output current per pin
Description
Condition
—
—
—
—
Minimum
–0.50
–25
(2)(3)(4)(5)
(6)
Maximum
2.46
25
125
150
Unit
V
mA
°C
°C
Operating junction temperature
Storage temperature (no bias)
–55
–65
Related Information
•
•
AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices
Provides the power sequencing requirements for Intel Arria 10 devices.
Power-Up and Power-Down Sequences, Power Management in Intel Arria 10 Devices chapter
Provides the power sequencing requirements for Intel Arria 10 devices.
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal
is equivalent to 100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
(2)
The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down
conditions is 10 mA.
Total current per LVDS I/O bank must not exceed 100 mA.
Voltage level must not exceed 1.89 V.
Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.
Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power
sequencing requirement. For more details, refer to
AN 692: Power Sequencing Considerations for Intel Cyclone
®
10 GX, Intel Arria
10, and Intel Stratix
®
10 Devices
and
Power Management in Intel Arria 10 Devices chapter.
This article is good, I recommend you to read it. It also gives the circuit calculation method. Multi-BOOST SEPIC circuit with low voltage stress[[i] This post was last edited by dontium on 2013-4-15 ...
[i=s]This post was last edited by dj madman on 2015-1-13 18:04[/i] [align=left] [size=4]ADuc7026 Learning-Time2[/size][/align][align=left][size=4] [/size][/align][align=left][size=4] [/size][/align][a...
Has anyone in the forum designed a solenoid valve driver board for an automotive ESP? I need help now. If anyone has done it, please help me. Thank you....
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