IS61DDPB41M36C1-500M3 datasheet, PDF

Datasheet> All Categories > storage> storage> IS61DDPB41M36C1-500M3

IS61DDPB41M36C1-500M3: DescriptionDDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165; Categorystorage storage; File Size919KB，32 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/

Download Datasheet Parametric View All

IS61DDPB41M36C1-500M3 Overview

DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165

IS61DDPB41M36C1-500M3 Parametric

Parameter Name	Attribute value
Objectid	8081880828
package instruction	LBGA,
Reach Compliance Code	unknown
Country Of Origin	Mainland China, Taiwan
ECCN code	3A991.B.2.A
YTEOL	7.15
Maximum access time	0.45 ns
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.89 V
Minimum supply voltage (Vsup)	1.71 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

Preview

Download Datasheet

View All

IS61DDPB42M18C/C1/C2

IS61DDPB41M36C/C1/C2

2Mx18, 1Mx36

36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

(2.5 Cycle Read Latency)

FEATURES



1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid

window.

Common I/O read and write ports.

Synchronous pipeline read with self-timed late write

operation.

Double Data Rate (DDR) interface for read and write

input ports.

2.5 cycle read latency.

Fixed 4-bit burst for read and write operations.

Clock stop support.

Two input clocks (K and K#) for address and control

registering at rising edges only.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

+1.8V core power supply and 1.5V to 1.8V VDDQ,

used with 0.75 to 0.9V VREF.

HSTL input and output interface.

Registered addresses, write and read controls, byte

writes, data in, and data outputs.

Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte write capability.

Fine ball grid array (FBGA) package:

13mm x 15mm & 15mm x 17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x user-

supplied precision resistor.

Data Valid Pin (QVLD).

ODT (On Die Termination) feature is supported

optionally on data inputs, K/K#, and BW

The end of top mark (C/C1/C2) is to define options.

IS61DDPB41M36C : Don’t care ODT function and

pin connection

IS61DDPB41M36C1: Option1

IS61DDPB41M36C2: Option2

Refer to more detail description at page 6 for each

ODT option.

APRIL 2016

DESCRIPTION

The 36Mb IS61DDPB41M36C/C1/C2 and IS61DDPB42M18C/C1/C2

are synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all

internal operations are self-timed. Refer to the

Timing Reference

Diagram for Truth Table

for a description of the basic operations of

these DDR-IIP (Burst of 4) CIO SRAMs.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.

The following are registered internally on the rising edge of

the K clock:



Read/write address



Read enable



Write enable



Byte writes



Data-in for first and third burst addresses



Data-out for second and fourth burst addresses

The following are registered on the rising edge of the K#

clock:



Byte writes



Data-in for second and fourth burst addresses



Data-out for first and third burst addresses

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after the

write address. The first data-in burst is clocked one cycle later

than the write command signal, and the second burst is timed

to the following rising edge of the K# clock. Two full clock

cycles are required to complete a write operation.

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the third rising

edge of the K# clock (starting two and half cycles later after

read command). The data-outs from the second burst are

updated with the fourth rising edge of the K clock where read

command receives at the first rising edge of K.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.



without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

IS61DDPB42M18C/C1/C2

IS61DDPB41M36C/C1/C2

Ball Descriptions

Symbol

K, K#

Type

Input

Description

Input clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of

phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

These balls cannot remain VREF level.

Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals are free running clocks and

do not stop when Q tri-states.

DLL disable and reset input: When low, this input causes the DLL to be bypassed and reset the

previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock

time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the

device can be operated at a frequency of up to 167MHz.

Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

CQ#.

Synchronous address inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. These inputs are ignored when device is deselected.

Data input and output signals. Input data must meet setup and hold times around the rising edges of

K and K# during WRITE operations. These pins drive out the requested data when the read

operation is active. Valid output data is synchronized to the respective CQ and CQ#.

See BALL CONFIGURATION figures for ball site location of individual signals.

The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.

The x36 device uses DQ0~DQ35.

Synchronous Read or Write input. When LD# is low, this input designates the access type (read

when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times

around edge of K.

Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition

includes address and read/write direction.

Synchronous byte writes: When low, these inputs cause their respective byte to be registered and

written during WRITE cycles. These signals are sampled on the same edge as the corresponding

data and must meet setup and hold times around the rising edges of K and K# for each of the two

rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffers.

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating

Conditions for range.

Ground of the device

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball

to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance

mode. This ball cannot be connected directly to VSS or left unconnected.

In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.

The ODT range is selected by ODT control input.

IEEE 1149.1 input pins for JTAG

IEEE 1149.1 output pins for JTAG

No connect: These signals should be left floating or connected to ground to improve package heat

dissipation.

ODT control; Refer to SRAM features for the details.

CQ, CQ#

Output

Doff#

Input

QVLD

Output

Input

DQ0 - DQn

Bidir

R/W#

LD#

Input

reference

Power

Ground

REF

DDQ

Input

TMS, TDI, TCK

TDO

ODT

Input

Output

N/A

Input

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

IS61DDPB42M18C/C1/C2

IS61DDPB41M36C/C1/C2

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is

presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write

burst address follows next, registered by the rising edge of K#.

The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array

on the third write cycle. A read cycle to the last two write address produces data from the write buffers. Similarly, a

read address followed by the same write address produces the latest write data. The SRAM maintains data coherency.

During a write, the byte writes independently control which byte of any of the two burst addresses is written. (See

X18/X36 Write Truth Tables

and

Timing Reference Diagram for Truth Table)

Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM to adjust

its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the

SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee

impedance matching is between 175Ω and 350Ω at V

DDQ

=1.5V. The RQ resistor should be placed less than two inches

away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ should not be

connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in

supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances

values. The final impedance value is achieved within 1024clock cycles.

Valid Data Indicator (QVLD)

A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with

the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle

before the final valid read data arrives.

Delay Locked Loop (DLL)

Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to

enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match

the clock frequency. Therefore device can have stable output over the temperature and voltage variation.

DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the

AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL

off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy

QUAD mode.

The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#

for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is

not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being

reset, it gets locked after 2048 cycles of stable clock.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

03/23/2016

Recommended Resources

GT-JDG1 protector basic circuit

GCA 20A/180V silicon rectifier charger circuit

Example circuit diagram of switching power supply using μPC1943,1944

555 should flow voltage too high, too low monitoring circuit 1

Frequency and time signal generator circuit

6OXT(1.0) computer motherboard circuit diagram_12

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components