5962R9662201V9A datasheet, PDF

Datasheet> All Categories > logic> logic> 5962R9662201V9A

5962R9662201V9A: Description4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14; Categorylogic logic; File Size73KB，9 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

Download Datasheet Parametric Compare View All

5962R9662201V9A Overview

4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14

5962R9662201V9A Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	DIE
package instruction	DIE-14
Contacts	14
Reach Compliance Code	unknown
series	4000/14000/40000
JESD-30 code	S-XUUC-N14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	2590000 Hz
Number of digits	1
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	UNSPECIFIED
encapsulated code	DIE
Encapsulate equivalent code	DIE OR CHIP
Package shape	SQUARE
Package form	UNCASED CHIP
power supply	5/15 V
propagation delay (tpd)	405 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	NO LEAD
Terminal location	UPPER
total dose	100k Rad(Si) V
Trigger type	POSITIVE EDGE
minfmax	3.5 MHz
Base Number Matches	1

Preview

Download Datasheet

View All

CD4013BMS

December 1992

CMOS Dual ‘D’-Type Flip-Flop

Pinout

Q1 1

14 VDD

13 Q2

12 Q2

11 CLOCK 2

10 RESET 2

9 D2

8 SET 2

Features

• High-Voltage Type (20V Rating)

• Set-Reset Capability

• Static Flip-Flop Operation - Retains State Indeﬁnitely

With Clock Level Either “High” Or “Low”

• Medium-Speed Operation - 16 MHz (typ.) Clock Toggle

Rate at 10V

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Q1 2

CLOCK 1 3

RESET 1 4

D1 5

SET 1 6

VSS 7

Functional Diagram

VDD

F/F2

F/F1

SET 1

CLOCK 1

Applications

RESET 1

• Registers

• Counters

SET 2

• Control Circuits

CLOCK 2

Description

CD4013BMS consists of two identical, independent data

type ﬂip-ﬂops. Each ﬂip-ﬂop has independent data, set,

reset, and clock inputs and Q and Q outputs. These devices

can be used for shift register applications, and, by

connecting Q output to the data input, for counter and toggle

applications. The logic level present at the D input is

transferred to the Q output during the positive going

transition of the clock pulse. Setting or resetting is

independent of the clock and is accomplished by a high level

on the set or reset line, respectively.

The CD4013BMS is supplied in these 14 lead outline pack-

ages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4Q

H1B

H3W

RESET 2

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number

3080

7-62

5962R9662201V9A Related Products

	5962R9662201V9A	5962R9662202VXC	5962R9662201VCC	5962R9662201VXC
Description	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, FP-14	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14	4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14
Parts packaging code	DIE	DFP	DIP	DFP
package instruction	DIE-14	DFP, FL14,.3	CERAMIC, DIP-14	DFP, FL14,.3
Contacts	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown
series	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000
JESD-30 code	S-XUUC-N14	R-CDFP-F14	R-CDIP-T14	R-CDFP-F14
JESD-609 code	e0	e4	e4	e4
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Sup	2590000 Hz	2590000 Hz	2590000 Hz	2590000 Hz
Number of digits	1	1	1	1
Number of functions	2	2	2	2
Number of terminals	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIE	DFP	DIP	DFP
Encapsulate equivalent code	DIE OR CHIP	FL14,.3	DIP14,.3	FL14,.3
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	UNCASED CHIP	FLATPACK	IN-LINE	FLATPACK
power supply	5/15 V	5/15 V	5/15 V	5/15 V
propagation delay (tpd)	405 ns	405 ns	405 ns	405 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	18 V	18 V	18 V	18 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	GOLD	GOLD	GOLD
Terminal form	NO LEAD	FLAT	THROUGH-HOLE	FLAT
Terminal location	UPPER	DUAL	DUAL	DUAL
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
minfmax	3.5 MHz	2.59 MHz	2.59 MHz	2.59 MHz
Base Number Matches	1	1	1	1
Maker	Renesas Electronics Corporation	-	Renesas Electronics Corporation	Renesas Electronics Corporation
MaximumI(ol)	-	0.00064 A	0.00064 A	0.00064 A
Terminal pitch	-	1.27 mm	2.54 mm	1.27 mm

Recommended Resources

Integrated synchronous RS flip-flop circuit

Color TV brightness limiting circuit

400V, 60W push-pull power circuit

Door opening alarm circuit diagram

Light control switch

Gas concentration meter circuit

Help, a novice has doubts about Linux drivers: Here are some codes in the driver for the four buttons on the 2440 board: struct button_irq_desc { int irq; int pin; int pin_setting; int number; char *name; }; static struct button_irq_desc button_ir...; mamh Linux and Android

I want to ask for help on what tests are generally required for Zigbee product production lines?: I would like to ask you guys about zigbee terminal products, what kind of tests need to be done before shipment? Especially the factory-side tests? Thank you...; carina15 RF/Wirelessly

Pre-match training FAQ: Detailed explanation of ON Semiconductor's ultra-low power RSL10 Bluetooth SoC development board: [Live Details] Detailed Explanation of ON Semiconductor's Ultra-Low Power RSL10 Bluetooth SoC Development Board[Content Introduction] ON Semiconductor, Avnet and EEWorld have jointly provided the indu...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

How to start with PCB layout and wiring to avoid noise caused by improper switching power supply layout: [i=s]This post was last edited by qwqwqw2088 on 2021-9-29 10:17[/i]Share Analog Devices: How to start with PCB layout and routing to avoid noise caused by improper switching power supply layout"Noise ...; qwqwqw2088 PCB Design

Urgent! arm920T operating frequency problem: arm920T naked running software control hardware. In ADS, I wrote a while loop while (1) {a++} in the main function. I calculated the time and found that a can only increase to 6000000 in 10 seconds, t...; cyjszone ARM Technology

A well-known communication company in Beijing is recruiting DSP software engineers: DSP Software Engineer Annual Salary 16-19W Job Responsibilities: 1. Responsible for the verification and implementation of the physical layer algorithm of the wireless system products of the broadband...; e1065037772 Recruitment

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components