P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
1
Z86E33/733/E34
Z86E43/743/E44
CMOS Z8
®
OTP M
ICROCONTROLLERS
FEATURES
Device
Z86E33
Z86733
Z86E34
Z86E43
Z86743
Z86E44
ROM
(KBytes)
4
8
16
4
8
16
RAM*
(Bytes)
237
237
237
236
236
236
I/O
Lines
24
24
24
32
32
32
Speed
(MHz)
16
16
16
16
16
16
s
1
Programmable Crystal Oscillator, EPROM Protect,
RAM Protect, Auto Latch Disable, Permanent WDT,
32 KHz Oscillator, and EPROM /Test Mode Disable
Fast Instruction Pointer: 0.6
µ
s
Two Standby Modes: STOP and HALT
24/32 Input and Output Lines
Digital Inputs CMOS Levels, Schmitt-Triggered
Software Programmable Low EMI Mode
Two Programmable 8-Bit Counter/Timers Each with a 6-
Bit Programmable Prescaler
Six Vectored, Priority Interrupts from Six Different
Sources
Auto Latches
Auto Power-On Reset (POR)
Two Comparators
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
s
s
s
s
s
Note:
*General-Purpose
s
s
s
Standard Temperature (V
CC
= 3.5V to 5.5V)
s
Extended Temperature (V
CC
= 4.5V to 5.5V)
28-Pin DIP/SOIC/PLCC Packages (E33/733/E34)
40-Pin DIP Package (E43/743/E44)
44-Pin PLCC/QFP Packages (E43/743/E44)
Software Enabled Watch-Dog Timer (WDT)
s
s
s
s
s
Push-Pull/Open-Drain Programmable on
Port 0, Port 1, and Port 2
Low-Power Consumption: 60 mW
s
s
s
GENERAL DESCRIPTION
The Z86E33/733/E34/E43/743/E44 8-bit CMOS One-Time
Programmable (OTP) microcontrollers are members of
Zilog's Z8
®
single-chip microcontroller family featuring en-
hanced wake-up circuitry, programmable Watch-Dog Tim-
ers, Low Noise EMI options, and easy hardware/software
system expansion capability.
Four basic address spaces support a wide range of mem-
ory configurations. The designer has easy access to regis-
ter mapped peripheral and I/O circuits.
For applications demanding powerful I/O capabilities, the
Z86E33/733/E34 have 24 pins and the Z86E43/743/E44
have 32 pins of dedicated input and output. These lines are
grouped into four ports, eight lines per port, and are config-
urable under software control to provide timing, status sig-
nals, and parallel I/O with or without handshake, and ad-
dress/data bus for interfacing external memory.
Notes:
All Signals with a preceding front slash, "/", are
active Low, e.g., B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
CP97DZ83300
PRELIMINARY
1
Z86E33/733/E34/E43/743/E44
CMOS Z8® OTP Microcontrollers
Zilog
P21
P22
P23
P24
/DS
NC
R//W
P25
P26
P27
P04
7
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P00
6
1
40
39
PLCC 44 - Pin
17
18
29
28
P30
P36
P37
P35
/RESET
R//RL
/AS
P34
P33
P32
P31
Figure 3. 44-Pin PLCC Pin Configuration
Standard Mode
Table 2. 44-Pin PLCC Pin Identification
Pin #
1-2
3-4
5
6-10
11
12
13
14-16
17-19
20-21
22
23-24
25-26
27
28
29-31
32
Symbol
GND
P12-P13
P03
P20-P24
/DS
NC
R//W
P25-P27
P04-P06
P14-P05
P07
VCC
P16-P17
XTAL2
XTAL1
P31-P33
P34
Function
Direction
Pin #
33
34
35
36
37
38
39
40-41
42-43
44
P05
P06
P14
P15
P07
VCC
VCC
P16
P17
XTAL2
XTAL1
Table 2. 44-Pin PLCC Pin Identification
Symbol
/AS
R//RL
/RESET
P35
P37
P36
P30
P00-P01
P10-P11
P02
Function
Address Strobe
ROM/ROMless
select
Reset
Port 3, Pin 5
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
Direction
Output
Input
Input
Output
Output
Output
Input
In/Output
In/Output
In/Output
Ground
Port 1, Pins 2,3 In/Output
Port 0, Pin 3
In/Output
Port 2, Pins
In/Output
0,1,2,3,4
Data Strobe
Output
No Connection
Read/Write
Output
Port 2, Pins 5,6,7In/Output
Port 0, Pins 4,5,6In/Output
Port 1, Pins 4,5 In/Output
Port 0, Pin 7
In/Output
Power Supply
Port 1, Pins 6,7 In/Output
Crystal Oscillator Output
Crystal Oscillator Input
Port 3, Pins 1,2,3Input
Port 3, Pin 4
Output
4
PRELIMINARY
CP97DZ83300
FPGA/CPLD
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EEWORLD
