UJA1168
Mini high-speed CAN system basis chip for partial networking
Rev. 2 — 16 April 2014
Product data sheet
1. General description
The UJA1168 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5/6 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for
a microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1168 can be operated in very low-current Standby and Sleep modes with bus and
local wake-up capability and supports ISO 11898-6 compliant CAN partial networking by
means of a selective wake-up function. The microcontroller supply is switched off in Sleep
mode. The UJA1168TK and UJA1168TK/FD versions contain a battery-related
high-voltage output (INH) for controlling an external voltage regulator, while the
UJA1168TK/VX and UJA1168TK/VX/FD are equipped with a 5 V sensor supply (VEXT).
A dedicated implementation of the partial networking protocol has been embedded into
the UJA1168/FD variants, UJA1168TK/FD and UJA1168TK/VX/FD (see
Section 6.8.1
for
further details on CAN FD). This function is called ‘FD-passive’ and is the ability to ignore
CAN FD frames while waiting for a valid wake-up frame in Sleep/Standby mode. This
additional feature of partial networking is the perfect fit for networks that support both CAN
FD and standard CAN 2.0 communications. It allows normal CAN controllers that do not
need to communicate CAN FD messages to remain in partial networking Sleep/Standby
mode during CAN FD communication without generating bus errors.
The UJA1168 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2, -5 and -6). Pending the release of the updated version of
ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry
are included. This implementation enables reliable communication in the CAN FD fast
phase at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1168 to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2, ISO 11898-5 and ISO 11898-6 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
NXP Semiconductors
UJA1168
Mini high-speed CAN system basis chip for partial networking
No ‘false’ wake-ups due to CAN FD frame detection in UJA1168TK/FD and
UJA1168TK/VX/FD
2.2 Designed for automotive applications
8
kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6
kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins, the sensor
supply output VEXT and on pins BAT and WAKE
CAN bus pins short-circuit proof to
58
V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby and Sleep modes with full wake-up capability
Leadless HVSON14 package (3.0 mm
4.5 mm) with improved Automated Optical
Inspection (AOI) capability and low thermal resistance
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.3 Low-drop voltage regulator for 5 V microcontroller supply (V1)
5 V nominal output;
2
% accuracy
100 mA output current capability
Current limiting above 150 mA
On-resistance of 5
(max)
Support for microcontroller RAM retention down to a battery voltage of 2 V
Undervoltage reset with selectable detection thresholds: 60 %, 70 %, 80 % or 90 % of
output voltage
Excellent transient response with a 4.7
F
ceramic output capacitor
Short-circuit to GND/overload protection on pin V1
Turned off in Sleep mode
2.4 Power Management
Standby mode featuring very low supply current; voltage V1 remains active to maintain
the supply to the microcontroller
Sleep mode featuring very low supply current with voltage V1 switched off
Remote wake-up capability via standard CAN wake-up pattern or via ISO 11898-6
compliant selective wake-up frame detection
Local wake-up via the WAKE pin
Wake-up source recognition
Local and/or remote wake-up can be disabled to reduce current consumption
High-voltage output (INH) for controlling an external voltage (UJA1168TK and
UJA1168TK/FD)
2.5 System control and diagnostic features
Mode control via the Serial Peripheral Interface (SPI)
Overtemperature warning and shutdown
Watchdog with independent clock source
UJA1168
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 16 April 2014
2 of 68
NXP Semiconductors
UJA1168
Mini high-speed CAN system basis chip for partial networking
Watchdog can be operated in Window, Timeout and Autonomous modes
Optional cyclic wake-up in watchdog Timeout mode
Watchdog automatically re-enabled when wake-up event captured
Watchdog period selectable between 8 ms and 4 s
Supports remote flash programming via the CAN bus
16-, 24- and 32-bit SPI for configuration, control and diagnosis
Bidirectional reset pin with variable power-on reset length to support a variety of
microcontrollers
Configuration of selected functions via non-volatile memory
2.6 Sensor supply voltage (pin VEXT of UJA1168TK/VX and
UJA1168TK/VX/FD)
5 V nominal output;
2
% accuracy
30 mA output current capability
Current limiting above 30 mA
Excellent transient response with a 4.7
F
ceramic output load capacitor
Protected against short-circuits to GND and to the battery
High ESD robustness of
6
kV according to IEC 61000-4-2
Can handle negative voltages as low as
18
V
3. Ordering information
Table 1.
Ordering information
Package
Name
UJA1168TK
UJA1168TK/VX
UJA1168TK/FD
[2]
UJA1168TK/VX/FD
[2]
[1]
[2]
UJA1168TK and UJA1168TK/FD contain a high-voltage output for controlling an external voltage regulator; UJA1168TK/X and
UJA1168TK/VX/FD include a 5 V/30 mA sensor supply.
UJA1168TK/FD and UJA1168TK/VX/FD can be configured to recognize CAN FD frames as valid data frames, but will not wake up when
a CAN FD frame is received (CAN FD-passive).
Type number
[1]
Description
plastic thermal enhanced very thin small outline package; no
leads; 14 terminals; body 3
4.5
0.85 mm
Version
SOT1086-2
HVSON14
UJA1168
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 16 April 2014
3 of 68
NXP Semiconductors
UJA1168
Mini high-speed CAN system basis chip for partial networking
4. Block diagram
UJA1168
10
7
BAT
HIGH VOLTAGE OUTPUT
(1)
INH
(1)
/VEXT
(2)
5 V SENSOR SUPPLY
(2)
5
5 V MICROCONTROLLER SUPPLY (V1)
3
RSTN
V1
WATCHDOG
RXD
TXD
4
1
HS-CAN
13
12
PARTIAL NETWORKING
CAN FD-passive
(3)
CANH
CANL
WAKE
9
WAKE-UP
SCK
SDI
SDO
SCSN
8
11
6
14
SPI
2
GND
015aaa254
(1) UJA1168TK and UJA1168TK/FD only.
(2) UJA1168TK/VX and UJA1168TK/VX/FD only.
(3) UJA1168TK/FD and UJA1168TK/VX/FD only.
Fig 1.
Block diagram of UJA1168
UJA1168
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 16 April 2014
4 of 68
NXP Semiconductors
UJA1168
Mini high-speed CAN system basis chip for partial networking
5. Pinning information
5.1 Pinning
terminal 1
index area
TXD
GND
V1
RXD
RSTN
SDO
INH/VEXT
(1)
1
2
3
4
5
6
7
14 SCSN
13 CANH
12 CANL
UJA1168
11 SDI
10 BAT
9
8
015aaa253
WAKE
SCK
Transparent top view
(1) INH in the UJA1168TK and UJA1168TK/FD; VEXT in the UJA1168TK/VX and UJA1168TK/VX/FD
Fig 2.
Pin configuration diagram
5.2 Pin description
Table 2.
Symbol
TXD
GND
V1
RXD
RSTN
SDO
INH
VEXT
SCK
WAKE
BAT
SDI
CANL
CANH
SCSN
[1]
Pin description
Pin
1
2
[1]
3
4
5
6
7
7
8
9
10
11
12
13
14
Description
transmit data input
ground
5 V microcontroller supply voltage
receive data output; reads out data from the bus lines
reset input/output
SPI data output
high-voltage output for switching external regulators (UJA1168TK and
UJA1168TK/FD only)
sensor supply voltage (UJA1168TK/VX and UJA1168TK/VX/FD only)
SPI clock input
local wake-up input
battery supply voltage
SPI data input
LOW-level CAN bus line
HIGH-level CAN bus line
SPI chip select input
The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
SBC via the printed circuit board. For enhanced thermal and electrical performance, it is recommended to
solder the exposed die pad to GND.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
UJA1168
Product data sheet
Rev. 2 — 16 April 2014
5 of 68
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