The V386 is an ideal LVDS receiver that converts 4-pair
LVDS data streams into parallel 28 bits of CMOS/TTL
data with bandwidth up to 2.38 Gbps throughput or
297.5 Mbytes per second.
This chip is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL
interfaces through very low-swing LVDS signals.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Features
•
Packaged in a 56-pin TSSOP (Pb free available)
•
Converts 4-pair LVDS data streams into parallel 28
bits of CMOS/TTL data
•
Up to 2.38 Gbps throughput or 297.5 Megabytes/sec
bandwidth
•
Wide clock frequency range from 25 MHz to 85 MHz
(for lower frequency requirements, please use
V386-2)
Pin Assignments
D22
D23
D24
GND
D25
D26
D27
LVDSGND
RX0-
RX0+
RX1-
RX1+
LVDSVCC
LVDSGND
RX2-
RX2+
RCK-
RCK+
RX3-
RX3+
LVDSGND
PLLGND
PLLVCC
PLLGND
PWRDWN
CLKOUT
D0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
D21
D20
D19
GND
D18
D17
D16
VCC
D15
D14
D13
GND
D12
D11
D10
VCC
D9
D8
D7
GND
D6
D5
D4
D3
VCC
D2
D1
•
•
•
•
•
•
•
•
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Falling edge clock triggered outputs
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Pin and function compatible with the National
DS90CF386, THine THC63LVDF84, TI
SN65LVDS94
Block Diagram
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RCK+
RCK-
PWRDWN
PLL
LVDS to TTL
De-serializer
8
8
8
RED
GREEN
BLUE
HSYNC
VSYNC
DATA ENABLE
CONTROL
CLOCK
V386
56-pin TSSOP
V386
V386 Datasheet
1
10/20/04
Revision 1.7
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-B
IT
LVDS R
ECEIVER FOR
V
IDEO
Pin Descriptions
Pin
Type
LVDS Differential
Input
Data Output
Pin
Count
10
Pins
9, 10, 11, 12, 15, 16, 17,
18, 19, 20
1, 2, 3, 5, 6, 7, 27, 29,
30, 32, 33, 34, 35, 37,
38, 39, 41, 42, 43, 45,
46, 47, 49, 50, 51, 53,
54, 55
26
13, 23, 31, 40, 48, 56
Pin Description/Name
8 pins (4 pairs) for Data inputs (RX0+, RX0- ; RX1+, RX1- ; RX2+,
RX2- ;RX3+, RX3-)
2 pins (1 pair) for Clock Inputs (RCK+, RCK-)
Data outputs on pins D0 through D27
28
Clock Output
VCC
1
6
CLKOUT
1 pin for LVDS input pairs (LVDSVCC)
1 pin for PLL (PLLVCC)
4 pins for Logic and Data outputs (VCC)
Power-down control input (PWRDWN) Active low
3 pins for LVDS input pairs (LVDSGND)
2 pins for PLL (PLLGND)
5 pins for Logic and Data outputs (GND)
Power Down
Ground
1
10
25
4, 8, 14, 21, 22, 24, 28,
36, 44, 5
External Components
The V386 require no external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V386. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VCC
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature (20 seconds max.)
Maximum Package Power
Package Derating
-0.3 V to +4 V
-0.3 V to (VCC+0.3 V)
-0.3 V to (VCC+0.3 V)
0 to +70°C
-65 to +150°C
150°C
260°C
1.61 W (V386)
12.4 mW/°C above +25°C
15 mW/°C above +25°C
Rating
V386 Datasheet
2
10/20/04
Revision 1.7
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-B
IT
LVDS R
ECEIVER FOR
V
IDEO
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (Ta)
3.3 V Supply Voltage (VCC)
CMOS/TTL Output Load (C
L
)
Receiver Input Range (V
IN
)
Supply Noise Voltage (V
N
)
0
Min.
0
3
Typ.
25
3.3
Max.
+70
3.6
8
2.4
100
Units
°C
V
pF
V
mVpp
Electrical Characteristics
VDD=3.3 V ±10%,
Ambient temperature 0 to +70°C
Parameter
CMOS/TTL DC Specifications
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
Output Short Circuit Current
LVDS Receiver DC Specifications
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Receiver Supply Current
Receiver Supply Current (worst case)
I
CCRW
C
L
= 8 pF, worst case pattern
(V386), f = 65 MHz
C
L
= 8 pF, worst case pattern
(V386), f = 85 MHz
Receiver Supply Current (16
Grayscale)
I
CCRG
C
L
= 8 pF, 16 Grayscale pattern,
f = 65 MHz
C
L
= 8 pF, 16 Grayscale pattern,
f = 85 MHz
Receiver Supply Current (Power
Down)
Receiver Switching Characteristics
CMOS Low-to-High Transition Time
for Data
CMOS Low-to-High Transition Time
for Data
DLHT
DHLT
20% to 80% VCC
80% to 20% VCC
2
1.8
6
6
ns
ns
I
CCRZ
Power_Down = Low,
Receiver outputs stay low
during Power-down mode
121
140
72
82
400
mA
mA
mA
mA
µA
V
TH
V
TL
I
IN
V
IN
= +2.4 V, VCC = 3.6 V
V
IN
= 0V, VCC = 3.6 V
V
CM
= +1.2 V
-100
±10
±10
+100
mV
mV
µA
µA
V
IH
V
IL
V
OH
V
OL
I
IN
I
OS
I
OH
= -4 mA
I
OL
= 2 mA
0<V
IN
<VCC
V
OUT
= 0V
2.0
GND
2.4
VCC
0.8
VCC
0.4
±10
-60
V
V
V
V
µA
mA
Symbol
Conditions
Min.
Typ.
Max.
Units
V386 Datasheet
3
10/20/04
Revision 1.7
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-B
IT
LVDS R
ECEIVER FOR
V
IDEO
Parameter
CMOS Low-to-High Transition Time
for Clock
CMOS Low-to-High Transition Time
for Clock
CLKOUT period
CLKOUT High Time
CLKOUT Low Time
Data Setup to CLKOUT
Data Hold to CLKOUT
RCK+/- to CLKOUT Delay
Receiver PLL Setup Time
Receiver Power Down Delay
Receiver Input Strobe Position for
Bit0
Receiver Input Strobe Position for
Bit1
Receiver Input Strobe Position for
Bit2
Receiver Input Strobe Position for
Bit3
Receiver Input Strobe Position for
Bit4
Receiver Input Strobe Position for
Bit5
Receiver Input Strobe Position for
Bit6
RxIn Skew Margin (see note and
Figure 8)
Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
Rskm
At 2.0 V
At 0.8 V
At 2.0 V
At 0.8 V
Conditions
20% to 80% VCC
80% to 20% VCC
Min.
Typ.
2
1.8
Max.
6
6
40
Units
ns
ns
ns
ns
ns
ns
ns
11.76
4.5
4
3.5
3.5
5.5
7
5
5
25
25
At 85 MHz
9.5
10
10
ns
ms
µs
ns
ns
ns
ns
ns
ns
ns
ps
ps
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 85 MHz, T = 11.76 ns
At 65 MHz, T = 15.38 ns
0.49
2.17
3.85
5.53
7.21
8.89
10.57
300
500
0.84
2.52
4.2
5.88
7.56
9.24
10.92
1.19
2.87
4.55
6.23
7.91
9.59
11.27
Note: The skew margins mean the maximum timing tolerance between the clock and data channel when
the receiver still works well. This margin takes into acount the receiver input setup and hold time, and
internal clock jitter (i.e., internal data sampling window - RSPos). Thyis margin allows for LVDS transmitter
pulse position, interconnect skew, inter-symbol interference and intrinsic channel mismatch which will
cause the skew between clock (RC+ and RCK-) and data (RX[n]+ and RX[n]- ; n =0, 1, 2, 3) channels.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
θ
JA
θ
JA
θ
JA
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
84
76
67
50
Max.
Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
θ
JC
V386 Datasheet
4
10/20/04
Revision 1.7
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-B
IT
LVDS R
ECEIVER FOR
V
IDEO
Timing Diagrams
CLKIN/CLKOUT
ODD Data In/Data Out
EVEN Data In/Data Out
T
Figure 1a. “Worst Case” Test Pattern
CLKOUT
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4-7, 12-15, 20-23
D24-27
Figure 1b. 16-Grayscale Test-Pattern Waveforms
80%
20%
DLHT
80%
20%
DLHT
CMOS/TTL Output
8 pF
Figure 2. V386 CMOS/TTL Output Load and Transition Time
V386 Datasheet
5
10/20/04
Revision 1.7
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
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