A54SX16TQG176 datasheet, PDF - EEWORLD Datasheet

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A54SX16TQG176: DescriptionFPGA, 1452 CLBS, 16000 GATES, 240MHz, PQFP176, 1.40 MM HEIGHT, MO-136, TQFP-176; CategoryProgrammable logic devices Programmable logic; File Size416KB，57 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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A54SX16TQG176 Overview

FPGA, 1452 CLBS, 16000 GATES, 240MHz, PQFP176, 1.40 MM HEIGHT, MO-136, TQFP-176

A54SX16TQG176 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	176
Reach Compliance Code	compliant
Other features	CAN ALSO BE OPERATED AT 3.3V
maximum clock frequency	240 MHz
Combined latency of CLB-Max	0.9 ns
JESD-30 code	S-PQFP-G176
JESD-609 code	e3
length	24 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1452
Equivalent number of gates	16000
Number of terminals	176
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1452 CLBS, 16000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	24 mm
Base Number Matches	1

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v3.1

54SX Family FPGAs

Le a di ng E dg e P er f or m a nc e

F ea t u r es

• 320 MHz Internal Performance

• 3.7 ns Clock-to-Out (Pin-to-Pin)

• 0.1 ns Input Set-Up

• 0.25 ns Clock Skew

Sp e ci f ic at ion s

• 66 MHz PCI

• CPLD and FPGA Integration

• Single Chip Solution

• 100% Resource Utilization with 100% Pin Locking

• 3.3V Operation with 5.0V Input Tolerance

• Very Low Power Consumption

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Debug capability with

Silicon Explorer II

• Boundary Scan Testing in Compliance with IEEE Standard

1149.1 (JTAG)

• Secure Programming Technology Prevents Reverse

Engineering and Design Theft

• 12,000 to 48,000 System Gates

• Up to 249 User-Programmable I/O Pins

• Up to 1080 Flip-Flops

• 0.35µ CMOS

S X P r od u c t P ro fi l e

A54SX08

Capacity

Typical Gates

System Gates

Logic Modules

Combinatorial Cells

Maximum User I/Os

Clocks

JTAG

PCI

Clock-to-Out

Input Set-Up (External)

Speed Grades

Temperature Grades

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

PBGA

FBGA

8,000

12,000

768

512

256

130

Yes

—

3.7 ns

0.8 ns

Std, –1, –2, –3

C, I, M

208

100

144, 176

—

144

A54SX16

16,000

24,000

1,452

924

528

175

Yes

—

3.9 ns

0.5 ns

Std, –1, –2, –3

C, I, M

—

208

100

176

—

A54SX16P

16,000

24,000

1,452

924

528

175

Yes

4.4 ns

0.5 ns

Std, –1, –2, –3

C, I, M

—

208

100

144, 176

—

A54SX32

32,000

48,000

2,880

1800

1,080

249

Yes

—

4.6 ns

0.1 ns

Std, –1, –2, –3

C, I, M

—

208

—

144, 176

313, 329

—

June 2003

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