50119-1198H datasheet, PDF - EEWORLD Datasheet

50119-1198H: DescriptionBoard Connector, 198 Contact(s), 3 Row(s), Male, Right Angle, 0.1 inch Pitch, Solder Terminal, Black Insulator, Receptacle; CategoryThe connector The connector; File Size341KB，4 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

50119-1198H Overview

Board Connector, 198 Contact(s), 3 Row(s), Male, Right Angle, 0.1 inch Pitch, Solder Terminal, Black Insulator, Receptacle

Parameter Name	Attribute value
Objectid	1152948326
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	9.1
Other features	OPTIONAL POLARIZATION
Board mount options	HOLE .099-.111
body width	0.485 inch
subject depth	0.827 inch
body length	7.35 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	AU ON NI
Contact completed and terminated	GOLD
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
contact mode	RECTANGULAR
Contact resistance	20 mΩ
Contact style	SQ PIN-SKT
Dielectric withstand voltage	1000VAC V
Insulation resistance	1000000000 Ω
Insulator color	BLACK
insulator material	GLASS FILLED POLYPHENYLENE SULFIDE
Plug contact pitch	0.1 inch
Match contact row spacing	0.1 inch
Installation method	RIGHT ANGLE
Installation type	BOARD
Number of connectors	ONE
PCB row number	3
Number of rows loaded	3
Maximum operating temperature	125 °C
Minimum operating temperature	-65 °C
PCB contact pattern	RECTANGULAR
PCB contact row spacing	2.54 mm
Plating thickness	30u inch
polarization key	POLARIZED KEY
Rated current (signal)	1 A
Guideline	UL, CSA
Terminal length	0.18 inch
Terminal pitch	2.54 mm
Termination type	SOLDER
Total number of contacts	198

Analog Electronics Course Selection Test: Watch the courses on the course list...; amperhong TI Technology Forum

About SPI mode setting: For SPI communication, there are only four pins: MOSI, MISO, CS, and CLK. SPI has four modes. So how do you set the various modes when using SPI? There are no clock polarity and phase pins?...; shijizai 51mcu

[FPGA Design Tips] Several concepts about FPGA clocks: delay, intermediate state and speed: InWhen the delay of data transfer between registers exceeds one clock cycle, the downstream register cannot sample the upstream data given in the current clock cycle in the next clock cycle, and an er...; eeleader FPGA/CPLD

Is there anyone who has ported the FLASH player to WINCE?: As the title says, if anyone has this question, please contact QQ: 414858335...; eddy326 Embedded System

Summary of works participating in the "Willful DIY" activity: [font=微软雅黑][size=3]This post is a collection of works participating in the "任性DIY" event. If you haven't participated in the event yet, hurry up and join us! [/size][/font][font=微软雅黑][size=3] [/size][...; eric_wang DIY/Open Source Hardware

[Sipeed LicheeRV 86 Panel Review] 14. lvgl displays images and local time: [i=s]This post was last edited by sonicfirr on 2022-4-25 21:03[/i]This article records the process of using the lvgl framework to display pictures, and also obtains the local time of the system and di...; sonicfirr Domestic Chip Exchange

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components