64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
DDR SDRAM
DIMM
Features
• JEDEC standard 184-pin, unbuffered dual in-line
memory module (DDR DIMM)
• Utilizes 266 MT/s and 333MT/s DDR SDRAM
components
• Fast data transfer rates: PC2100 or PC2700
• 64MB (8 Meg x 64), 128MB (16 Meg x 64), and
256MB (32 Meg x 64)
• V
DD
= V
DD
Q= +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes: 15.625µs
(64MB); 7.8125µs (128MB, 256MB) maximum
average periodic refresh interval.
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
MT4VDDT864A – 64MB
MT4VDDT1664A – 128MB
MT4VDDT3264A – 256MB
Figure 1: 184-Pin DIMM (MO–206)
OPTIONS
MARKING
• Operating Temperature Range
Commercial (0°C to +70°C)
None
1
Industrial (-40°C to +85°C)
I
• Package
184-pin DIMM (Standard)
G
1
184-Pin DIMM (Lead-free)
Y
2
• Memory Clock, Speed, CAS Latency
6ns, 333 MT/s (167 MHz), CL = 2.5
-335
7.5ns, 266 MT/s (133 MHz), CL = 2
-262
1
7.5ns, 266 MT/s (133 MHz), CL = 2
-26A
1
7.5ns, 266 MT/s (133 MHz), CL = 2.5
-265
• PCB
1.25in. (31.75mm)
See page 2 note
NOTE:
1. Consult Micron for product availability.
2. CL = Device CAS (READ) Latency.
Table 1:
Address Table
64MB
128MB
256MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (8 Meg x 16)
512 (A0–A8)
1 (S0#)
8K
8K
8K(A0–A12)
8K(A0–A12)
4 (BA0, BA1)
4 (BA0, BA1)
256Mb (16 Meg x 16) 512Mb (32 Meg x 16)
512 (A0–A8)
1K (A0–A9)
1 (S0#)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
184-Pin DIMM Pinouts
Front View
U1
U2
U4
U5
U6
PIN 1
PIN 52
PIN 53
PIN 92
Back View
No Components This Side of Module
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#,
RAS#
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK and CK# are differential clock inputs. All address
and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers, and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE
POWER-DOWN (row ACTIVE in any device bank). CKE is
synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit
and for disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V
DD
is applied and until CKE is first brought HIGH. After
CKE is brought HIGH, it becomes an SSTL_2 input only.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
63, 65, 154
16, 17, 75, 76, 137, 138
21
Input
157
S0#
Input
52, 59
BA0, BA1
Input
pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 5:
Pin Descriptions
SYMBOL
A0–A11
(64MB)
A0–A12
(128MB, 256MB)
TYPE
Input
DESCRIPTION
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0 and BA1 define
which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER
command.
Serial Presence-Detect Data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Data Write Mask: DM LOW allows WRITE operation. DM
HIGH blocks WRITE operation. DM lines do not affect READ
operation.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE
data. Used to capture data.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
27, 29, 32, 37, 41, 43,
48, 115
(128MB, 256MB),
118,
122, 125, 130, 141
91
SDA
Input/
Output
Input
Input
Input/
Output
Input/
Output
Input/
Output
92
181, 182, 183
97, 107, 119, 129, 149, 159,
169, 177
5, 14, 25, 36, 56, 67, 78, 86
SCL
SA0–SA2
DM0–DM7
DQS0–DQS7
2, 4, 6, 8, 12, 13, 19, 20, 23, 24,
28, 31, 33, 35, 39, 40, 53, 55,
57, 60, 61, 64, 68, 69, 72, 73,
79, 80, 83, 84, 87, 88, 94, 95,
98, 99, 105, 106, 109, 110, 114,
117, 121, 123, 126, 127, 131,
133, 146, 147, 150, 151, 153,
155, 161, 162, 165, 166, 170,
171, 174, 175, 178, 179
1
15, 22, 30, 54, 62, 77, 96, 104,
112, 128, 136, 143, 156, 164,
172, 180
7, 38, 46, 70, 85, 108, 120, 148,
168
3, 11, 18, 26, 34, 42, 50, 58, 66,
74, 81, 89, 93, 100, 116, 124,
132, 139, 145, 152, 160, 176
184
9, 71, 82, 90, 101, 102, 103,
113, 115 (64MB), 158, 163, 167,
173
10, 44, 45, 47, 49, 51, 111, 134,
135, 140, 142, 144
DQ0–DQ63
V
REF
V
DD
Q
Supply
Supply
SSTL_2 reference voltage.
DQ Power Supply: +2.5V ±0.2V.
V
DD
V
SS
Supply
Supply
Power Supply: +2.5V ±0.2V.
Ground.
V
DDSPD
NC
Supply
–
Serial EEPROM positive power supply: +2.3V to +3.6V.
No Connect: These pins should be left unconnected.
DNU
–
Do Not Use: These pins are not connected on this module but
are assigned pins on other modules in this product family.
pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
Analogue and Mixed Signal
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