PRELIMINARY DATA SHEET
µ
PD4811650 for Rev.E
16 M-BIT SYNCHRONOUS GRAM
256K-WORD BY 32-BIT BY 2-BANK
MOS INTEGRATED CIRCUIT
Description
The
µ
PD4811650 is a synchronous graphics memory (SGRAM) organized as 262,144 words
×
32 bits
×
2 banks
random access port.
This device can operate up to 143 MHz by using synchronous interface. Also, it has 8-column Block Write function
to improve capability in graphics system.
This product is packaged in 100-pin plastic TQFP (14
×
20 mm).
Features
•
262,144 words
×
32 bits
×
2 banks memory
•
Synchronous interface (Fully synchronous DRAM with all input signals are latched at rising edge of clock)
: Pulsed interface
: Automatic precharge and controlled precharge commands
: Ping-pong operation between the two internal memory banks
: Up to 143 MHz operation frequency
•
Possible to assert random column address in every cycle
•
Dual internal banks controlled by A10 (Bank Address: BA)
•
Byte control using DQM0 to DQM3 signals both in read and write cycle
•
8-column Block Write (BW) function
•
Persistent write per bit (WPB) function
•
Wrap sequence : Sequential / Interleave
•
Programmable burst length (1, 2, 4, 8 and full page)
•
Programmable /CAS latency (-A70R: 3, -A80, -A10, -A12: 2 and 3)
•
Power Down operation and Clock Suspend operation
•
Auto refresh (CBR refresh) or self refresh capability
•
Single 3.3 V
±
0.3 V power supply
•
LVTTL compatible inputs and outputs
•
100-pin Plastic TQFP (14
×
20 mm)
•
2,048 refresh cycles/32 ms
•
Burst termination by Precharge command
•
Burst termination by Burst stop command
5
Ordering Information
Part number
Cycle time
ns (MIN.)
7
8
10
12
Clock frequency
MHz (MAX.)
143
125
100
83
100-pin Plastic TQFP (14
×
20 mm)
Package
µ
PD4811650GF-A70R-9BT
µ
PD4811650GF-A80-9BT
µ
PD4811650GF-A10-9BT
µ
PD4811650GF-A12-9BT
The information in this document is subject to change without notice.
Document No. M13616EJ2V0DS00 (1st edition)
Date Published August 1998 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
1998
µ
PD4811650 for Rev. E
CONTENTS
1. Input/Output Pin Function ..... 7
2. Commands ..... 8
3. Simplified State Diagram ..... 12
4. Truth Table ..... 13
4.1 Command Truth Table ..... 13
4.2 DQM Truth Table ..... 13
4.3 CKE Truth Table ..... 14
4.4 Operative Command Table ..... 15
4.5 Command Truth Table for CKE ..... 22
4.6 Command Truth Table for Two Banks Operation ..... 23
5. Initialization ..... 24
6. Programming the Mode Register ..... 25
7. Mode Register ..... 26
7.1 Burst Length and Sequence ..... 27
8. Programming the Special Register ..... 28
8.1 Color Register ..... 28
8.2 Mask Register ..... 28
8.3 Special Register ..... 28
9. Address Bits of Bank Address and Precharge ..... 29
10. Precharge ..... 30
11. Auto Precharge ..... 31
11.1 Read with Auto Precharge ..... 31
11.2 Write with Auto Precharge ..... 32
11.3 Block Write with Auto Precharge ..... 33
12. Write/Block Write with Write Per Bit ..... 34
12.1 Write Per Bit ..... 34
13. Block Write ..... 34
13.1 Block Write ..... 34
13.2 Column Mask ..... 35
Preliminary Data Sheet
5
京公网安备 11010802033920号
EEWORLD
