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GTLP8T306MTCX_NL

Description
Bus Transceiver, GTLP Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, 4.40 MM, MO-153, TSSOP-24
Categorylogic    logic   
File Size55KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric View All

GTLP8T306MTCX_NL Overview

Bus Transceiver, GTLP Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, 4.40 MM, MO-153, TSSOP-24

GTLP8T306MTCX_NL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instruction4.40 MM, MO-153, TSSOP-24
Contacts24
Reach Compliance Codecompliant
Control typeCOMMON CONTROL
Counting directionBIDIRECTIONAL
seriesGTLP
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Logic integrated circuit typeBUS TRANSCEIVER
MaximumI(ol)0.05 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of ports2
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup8.3 ns
propagation delay (tpd)8.3 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
translateGTL/P & LVTTL
width4.4 mm
Base Number Matches1
GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver
September 1997
Revised December 2000
GTLP8T306
8-Bit LVTTL/GTLP Bus Transceiver
General Description
The GTLP8T306 is an 8-bit bus transceiver that provides
LVTTL to GTLP signal level translation. The device pro-
vides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (
<
1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal output edge-rate control and
is process, voltage, and temperature (PVT) compensated.
Its function is similar to BTL and GTL but with different out-
put levels and receiver thresholds. The GTLP output LOW
level is typically less than 0.5V, the output HIGH level is
1.5V and the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced CMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
5V over voltage tolerance on LVTTL ports
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP8T306MTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS500051
www.fairchildsemi.com

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