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70V24S55GG

Description
Dual-Port SRAM, 4KX16, 55ns, CMOS, CPGA84, 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-84
Categorystorage    storage   
File Size211KB,25 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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70V24S55GG Overview

Dual-Port SRAM, 4KX16, 55ns, CMOS, CPGA84, 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-84

70V24S55GG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instruction1.120 X 1.120 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-84
Contacts84
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time55 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-CPGA-P84
JESD-609 codee3
length30.6705 mm
memory density65536 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of ports2
Number of terminals84
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4KX16
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA84M,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum standby current0.005 A
Minimum standby current3 V
Maximum slew rate0.18 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width30.6705 mm
Base Number Matches1
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
Features
IDT70V35/34S/L
IDT70V25/24S/L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35/34
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25/24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
Low-power operation
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Active: 415mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
µ
W (typ.)
– IDT70V25/24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V25/24L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
Control
I/O
0L
-I/O
8L
(4)
BUSY
L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
Address
Decoder
13
A
12L
(1)
A
0L
MEMORY
ARRAY
13
Address
Decoder
A
12R
(1)
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L
(3)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5624 drw 01
M/S
NOTES:
1. A
12
is a NC for IDT70V34 and for IDT70V24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70V25/24.
5. I/O
8
x - I/O
15
x for IDT70V25/24.
OCTOBER 2008
1
DSC-5624/7
©2008 Integrated Device Technology, Inc.
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